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2f13163a84
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
52 lines
1.4 KiB
LLVM
52 lines
1.4 KiB
LLVM
; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s
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; rdar://9332258
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define float @test1(float %x, float %y) nounwind {
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entry:
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; CHECK-LABEL: test1:
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; CHECK: movi.4s v2, #128, lsl #24
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; CHECK: bit.16b v0, v1, v2
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%0 = tail call float @copysignf(float %x, float %y) nounwind readnone
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ret float %0
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}
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define double @test2(double %x, double %y) nounwind {
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entry:
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; CHECK-LABEL: test2:
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; CHECK: movi.2d v2, #0
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; CHECK: fneg.2d v2, v2
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; CHECK: bit.16b v0, v1, v2
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%0 = tail call double @copysign(double %x, double %y) nounwind readnone
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ret double %0
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}
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; rdar://9545768
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define double @test3(double %a, float %b, float %c) nounwind {
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; CHECK-LABEL: test3:
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; CHECK: fcvt d1, s1
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; CHECK: fneg.2d v2, v{{[0-9]+}}
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; CHECK: bit.16b v0, v1, v2
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%tmp1 = fadd float %b, %c
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%tmp2 = fpext float %tmp1 to double
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%tmp = tail call double @copysign( double %a, double %tmp2 ) nounwind readnone
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ret double %tmp
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}
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define float @test4() nounwind {
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entry:
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; CHECK-LABEL: test4:
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; CHECK: fcvt s0, d0
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; CHECK: movi.4s v[[CONST:[0-9]+]], #128, lsl #24
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; CHECK: bit.16b v{{[0-9]+}}, v0, v[[CONST]]
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%0 = tail call double (...)* @bar() nounwind
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%1 = fptrunc double %0 to float
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%2 = tail call float @copysignf(float 5.000000e-01, float %1) nounwind readnone
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%3 = fadd float %1, %2
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ret float %3
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}
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declare double @bar(...)
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declare double @copysign(double, double) nounwind readnone
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declare float @copysignf(float, float) nounwind readnone
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