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b9148f5d85
Summary: Extend cachepolicy operand in the new VMEM buffer intrinsics to supply information whether the buffer data is swizzled. Also, propagate this information to MIR. Intrinsics updated: int_amdgcn_raw_buffer_load int_amdgcn_raw_buffer_load_format int_amdgcn_raw_buffer_store int_amdgcn_raw_buffer_store_format int_amdgcn_raw_tbuffer_load int_amdgcn_raw_tbuffer_store int_amdgcn_struct_buffer_load int_amdgcn_struct_buffer_load_format int_amdgcn_struct_buffer_store int_amdgcn_struct_buffer_store_format int_amdgcn_struct_tbuffer_load int_amdgcn_struct_tbuffer_store Furthermore, disable merging of VMEM buffer instructions in SI Load/Store optimizer, if the "swizzled" bit on the instruction is on. The default value of the bit is 0, meaning that data in buffer is linear and buffer instructions can be merged. There is no difference in the generated code with this commit. However, in the future it will be expected that front-ends use buffer intrinsics with correct "swizzled" bit set. Reviewers: arsenm, nhaehnle, tpr Reviewed By: nhaehnle Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68200 llvm-svn: 373491
77 lines
2.9 KiB
YAML
77 lines
2.9 KiB
YAML
# RUN: llc -march=amdgcn -run-pass simple-register-coalescing -o - %s | FileCheck %s
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# Test that register coalescing does not allow a call to
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# LIS->getInstructionIndex with a DBG_VALUE instruction, which does not have
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# a slot index.
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# CHECK: %13.sub2:sgpr_128 = S_MOV_B32 0
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# CHECK: DBG_VALUE{{.*}} %13.sub2
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--- |
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define amdgpu_kernel void @test(i32 addrspace(1)* %out) { ret void }
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!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !4, producer: "llvm", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, retainedTypes: !4)
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!1 = !DILocalVariable(name: "a", scope: !2, file: !4, line: 126, type: !6)
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!2 = distinct !DISubprogram(name: "test", scope: !4, file: !4, line: 1, type: !3, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, unit: !0, retainedNodes: !5)
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!3 = !DISubroutineType(types: !4)
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!4 = !{null}
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!5 = !{!1}
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!6 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !7, size: 64, align: 32)
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!7 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)
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!8 = !DIExpression()
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!9 = !DILocation(line: 126, column: 9, scope: !2)
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...
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---
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name: test
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sgpr_64 }
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- { id: 1, class: sreg_32_xm0 }
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- { id: 2, class: sgpr_32 }
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- { id: 3, class: vgpr_32 }
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- { id: 4, class: sreg_64_xexec }
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- { id: 5, class: sreg_32_xm0_xexec }
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- { id: 6, class: sreg_32 }
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- { id: 7, class: sreg_32 }
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- { id: 8, class: sreg_32_xm0 }
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- { id: 9, class: sreg_64 }
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- { id: 10, class: sreg_32_xm0 }
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- { id: 11, class: sreg_32_xm0 }
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- { id: 12, class: sgpr_64 }
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- { id: 13, class: sgpr_128 }
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- { id: 14, class: sreg_32_xm0 }
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- { id: 15, class: sreg_64 }
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- { id: 16, class: vgpr_32 }
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- { id: 17, class: vreg_64 }
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- { id: 18, class: vgpr_32 }
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- { id: 19, class: vreg_64 }
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- { id: 20, class: vreg_64 }
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liveins:
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- { reg: '$sgpr0_sgpr1', virtual-reg: '%0' }
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- { reg: '$vgpr0', virtual-reg: '%3' }
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $vgpr0
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%3 = COPY killed $vgpr0
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%0 = COPY killed $sgpr0_sgpr1
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%4 = S_LOAD_DWORDX2_IMM %0, 9, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
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%5 = S_LOAD_DWORD_IMM killed %0, 13, 0, 0 :: (non-temporal dereferenceable invariant load 4 from `i32 addrspace(4)* undef`)
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%18 = V_ASHRREV_I32_e32 31, %3, implicit $exec
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undef %19.sub0 = COPY killed %3
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%19.sub1 = COPY killed %18
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%10 = S_MOV_B32 61440
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%11 = S_MOV_B32 0
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DBG_VALUE debug-use %11, debug-use $noreg, !1, !8, debug-location !9
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undef %12.sub0 = COPY killed %11
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%12.sub1 = COPY killed %10
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undef %13.sub0_sub1 = COPY killed %4
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%13.sub2_sub3 = COPY killed %12
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%20 = V_LSHL_B64 killed %19, 2, implicit $exec
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%16 = COPY killed %5
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BUFFER_STORE_DWORD_ADDR64 killed %16, killed %20, killed %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.out)
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S_ENDPGM 0
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...
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