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86e216695b
This makes the first stage DAG for @llvm.convert.to.fp16 an fptrunc, and correspondingly @llvm.convert.from.fp16 an fpext. The legalisation path is now uniform, regardless of the input IR: fptrunc -> FP_TO_FP16 (if f16 illegal) -> libcall fpext -> FP16_TO_FP (if f16 illegal) -> libcall Each target should be able to select the version that best matches its operations and not be required to duplicate patterns for both fptrunc and FP_TO_FP16 (for example). As a result we can remove some redundant AArch64 patterns. llvm-svn: 213507
252 lines
7.3 KiB
LLVM
252 lines
7.3 KiB
LLVM
; RUN: llc < %s -mtriple=arm64-apple-ios -asm-verbose=false | FileCheck %s
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define float @load0(i16* nocapture readonly %a) nounwind {
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; CHECK-LABEL: load0:
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; CHECK-NEXT: ldr [[HREG:h[0-9]+]], [x0]
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; CHECK-NEXT: fcvt s0, [[HREG]]
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; CHECK-NEXT: ret
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%tmp = load i16* %a, align 2
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%tmp1 = tail call float @llvm.convert.from.fp16.f32(i16 %tmp)
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ret float %tmp1
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}
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define double @load1(i16* nocapture readonly %a) nounwind {
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; CHECK-LABEL: load1:
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; CHECK-NEXT: ldr [[HREG:h[0-9]+]], [x0]
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; CHECK-NEXT: fcvt d0, [[HREG]]
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; CHECK-NEXT: ret
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%tmp = load i16* %a, align 2
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%conv = tail call double @llvm.convert.from.fp16.f64(i16 %tmp)
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ret double %conv
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}
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define float @load2(i16* nocapture readonly %a, i32 %i) nounwind {
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; CHECK-LABEL: load2:
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; CHECK-NEXT: ldr [[HREG:h[0-9]+]], [x0, w1, sxtw #1]
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; CHECK-NEXT: fcvt s0, [[HREG]]
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; CHECK-NEXT: ret
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%idxprom = sext i32 %i to i64
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%arrayidx = getelementptr inbounds i16* %a, i64 %idxprom
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%tmp = load i16* %arrayidx, align 2
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%tmp1 = tail call float @llvm.convert.from.fp16.f32(i16 %tmp)
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ret float %tmp1
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}
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define double @load3(i16* nocapture readonly %a, i32 %i) nounwind {
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; CHECK-LABEL: load3:
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; CHECK-NEXT: ldr [[HREG:h[0-9]+]], [x0, w1, sxtw #1]
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; CHECK-NEXT: fcvt d0, [[HREG]]
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; CHECK-NEXT: ret
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%idxprom = sext i32 %i to i64
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%arrayidx = getelementptr inbounds i16* %a, i64 %idxprom
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%tmp = load i16* %arrayidx, align 2
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%conv = tail call double @llvm.convert.from.fp16.f64(i16 %tmp)
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ret double %conv
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}
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define float @load4(i16* nocapture readonly %a, i64 %i) nounwind {
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; CHECK-LABEL: load4:
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; CHECK-NEXT: ldr [[HREG:h[0-9]+]], [x0, x1, lsl #1]
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; CHECK-NEXT: fcvt s0, [[HREG]]
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; CHECK-NEXT: ret
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%arrayidx = getelementptr inbounds i16* %a, i64 %i
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%tmp = load i16* %arrayidx, align 2
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%tmp1 = tail call float @llvm.convert.from.fp16.f32(i16 %tmp)
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ret float %tmp1
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}
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define double @load5(i16* nocapture readonly %a, i64 %i) nounwind {
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; CHECK-LABEL: load5:
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; CHECK-NEXT: ldr [[HREG:h[0-9]+]], [x0, x1, lsl #1]
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; CHECK-NEXT: fcvt d0, [[HREG]]
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; CHECK-NEXT: ret
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%arrayidx = getelementptr inbounds i16* %a, i64 %i
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%tmp = load i16* %arrayidx, align 2
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%conv = tail call double @llvm.convert.from.fp16.f64(i16 %tmp)
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ret double %conv
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}
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define float @load6(i16* nocapture readonly %a) nounwind {
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; CHECK-LABEL: load6:
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; CHECK-NEXT: ldr [[HREG:h[0-9]+]], [x0, #20]
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; CHECK-NEXT: fcvt s0, [[HREG]]
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; CHECK-NEXT: ret
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%arrayidx = getelementptr inbounds i16* %a, i64 10
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%tmp = load i16* %arrayidx, align 2
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%tmp1 = tail call float @llvm.convert.from.fp16.f32(i16 %tmp)
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ret float %tmp1
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}
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define double @load7(i16* nocapture readonly %a) nounwind {
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; CHECK-LABEL: load7:
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; CHECK-NEXT: ldr [[HREG:h[0-9]+]], [x0, #20]
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; CHECK-NEXT: fcvt d0, [[HREG]]
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; CHECK-NEXT: ret
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%arrayidx = getelementptr inbounds i16* %a, i64 10
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%tmp = load i16* %arrayidx, align 2
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%conv = tail call double @llvm.convert.from.fp16.f64(i16 %tmp)
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ret double %conv
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}
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define float @load8(i16* nocapture readonly %a) nounwind {
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; CHECK-LABEL: load8:
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; CHECK-NEXT: ldur [[HREG:h[0-9]+]], [x0, #-20]
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; CHECK-NEXT: fcvt s0, [[HREG]]
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; CHECK-NEXT: ret
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%arrayidx = getelementptr inbounds i16* %a, i64 -10
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%tmp = load i16* %arrayidx, align 2
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%tmp1 = tail call float @llvm.convert.from.fp16.f32(i16 %tmp)
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ret float %tmp1
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}
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define double @load9(i16* nocapture readonly %a) nounwind {
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; CHECK-LABEL: load9:
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; CHECK-NEXT: ldur [[HREG:h[0-9]+]], [x0, #-20]
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; CHECK-NEXT: fcvt d0, [[HREG]]
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; CHECK-NEXT: ret
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%arrayidx = getelementptr inbounds i16* %a, i64 -10
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%tmp = load i16* %arrayidx, align 2
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%conv = tail call double @llvm.convert.from.fp16.f64(i16 %tmp)
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ret double %conv
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}
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define void @store0(i16* nocapture %a, float %val) nounwind {
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; CHECK-LABEL: store0:
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: str h0, [x0]
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; CHECK-NEXT: ret
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%tmp = tail call i16 @llvm.convert.to.fp16.f32(float %val)
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store i16 %tmp, i16* %a, align 2
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ret void
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}
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define void @store1(i16* nocapture %a, double %val) nounwind {
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; CHECK-LABEL: store1:
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; CHECK-NEXT: fcvt h0, d0
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; CHECK-NEXT: str h0, [x0]
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; CHECK-NEXT: ret
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%conv = fptrunc double %val to float
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%tmp = tail call i16 @llvm.convert.to.fp16.f32(float %conv)
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store i16 %tmp, i16* %a, align 2
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ret void
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}
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define void @store2(i16* nocapture %a, i32 %i, float %val) nounwind {
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; CHECK-LABEL: store2:
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: str h0, [x0, w1, sxtw #1]
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; CHECK-NEXT: ret
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%tmp = tail call i16 @llvm.convert.to.fp16.f32(float %val)
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%idxprom = sext i32 %i to i64
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%arrayidx = getelementptr inbounds i16* %a, i64 %idxprom
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store i16 %tmp, i16* %arrayidx, align 2
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ret void
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}
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define void @store3(i16* nocapture %a, i32 %i, double %val) nounwind {
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; CHECK-LABEL: store3:
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; CHECK-NEXT: fcvt h0, d0
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; CHECK-NEXT: str h0, [x0, w1, sxtw #1]
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; CHECK-NEXT: ret
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%conv = fptrunc double %val to float
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%tmp = tail call i16 @llvm.convert.to.fp16.f32(float %conv)
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%idxprom = sext i32 %i to i64
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%arrayidx = getelementptr inbounds i16* %a, i64 %idxprom
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store i16 %tmp, i16* %arrayidx, align 2
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ret void
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}
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define void @store4(i16* nocapture %a, i64 %i, float %val) nounwind {
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; CHECK-LABEL: store4:
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: str h0, [x0, x1, lsl #1]
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; CHECK-NEXT: ret
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%tmp = tail call i16 @llvm.convert.to.fp16.f32(float %val)
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%arrayidx = getelementptr inbounds i16* %a, i64 %i
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store i16 %tmp, i16* %arrayidx, align 2
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ret void
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}
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define void @store5(i16* nocapture %a, i64 %i, double %val) nounwind {
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; CHECK-LABEL: store5:
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; CHECK-NEXT: fcvt h0, d0
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; CHECK-NEXT: str h0, [x0, x1, lsl #1]
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; CHECK-NEXT: ret
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%conv = fptrunc double %val to float
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%tmp = tail call i16 @llvm.convert.to.fp16.f32(float %conv)
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%arrayidx = getelementptr inbounds i16* %a, i64 %i
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store i16 %tmp, i16* %arrayidx, align 2
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ret void
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}
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define void @store6(i16* nocapture %a, float %val) nounwind {
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; CHECK-LABEL: store6:
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: str h0, [x0, #20]
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; CHECK-NEXT: ret
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%tmp = tail call i16 @llvm.convert.to.fp16.f32(float %val)
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%arrayidx = getelementptr inbounds i16* %a, i64 10
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store i16 %tmp, i16* %arrayidx, align 2
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ret void
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}
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define void @store7(i16* nocapture %a, double %val) nounwind {
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; CHECK-LABEL: store7:
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; CHECK-NEXT: fcvt h0, d0
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; CHECK-NEXT: str h0, [x0, #20]
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; CHECK-NEXT: ret
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%conv = fptrunc double %val to float
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%tmp = tail call i16 @llvm.convert.to.fp16.f32(float %conv)
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%arrayidx = getelementptr inbounds i16* %a, i64 10
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store i16 %tmp, i16* %arrayidx, align 2
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ret void
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}
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define void @store8(i16* nocapture %a, float %val) nounwind {
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; CHECK-LABEL: store8:
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: stur h0, [x0, #-20]
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; CHECK-NEXT: ret
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%tmp = tail call i16 @llvm.convert.to.fp16.f32(float %val)
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%arrayidx = getelementptr inbounds i16* %a, i64 -10
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store i16 %tmp, i16* %arrayidx, align 2
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ret void
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}
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define void @store9(i16* nocapture %a, double %val) nounwind {
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; CHECK-LABEL: store9:
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; CHECK-NEXT: fcvt h0, d0
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; CHECK-NEXT: stur h0, [x0, #-20]
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; CHECK-NEXT: ret
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%conv = fptrunc double %val to float
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%tmp = tail call i16 @llvm.convert.to.fp16.f32(float %conv)
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%arrayidx = getelementptr inbounds i16* %a, i64 -10
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store i16 %tmp, i16* %arrayidx, align 2
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ret void
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}
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declare i16 @llvm.convert.to.fp16.f32(float) nounwind readnone
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declare float @llvm.convert.from.fp16.f32(i16) nounwind readnone
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declare i16 @llvm.convert.to.fp16.f64(double) nounwind readnone
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declare double @llvm.convert.from.fp16.f64(i16) nounwind readnone
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