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5fca4ca5f9
memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. llvm-svn: 110785
18 lines
450 B
LLVM
18 lines
450 B
LLVM
; RUN: llc < %s -march=thumb -mattr=+v6 | FileCheck %s
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declare void @llvm.memory.barrier( i1 , i1 , i1 , i1 , i1 )
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define void @t1() {
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; CHECK: t1:
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; CHECK: blx {{_*}}sync_synchronize
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call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 true )
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ret void
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}
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define void @t2() {
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; CHECK: t2:
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; CHECK: blx {{_*}}sync_synchronize
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call void @llvm.memory.barrier( i1 false, i1 false, i1 false, i1 true, i1 false )
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ret void
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}
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