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9ebcb8b246
In a previous iteration of the pass, we would try to compensate for writeback by updating later instructions and/or inserting a SUBS to reset the base register if necessary. Since such a SUBS sets the condition flags it's not generally safe to do this. For now, only merge LDR/STRs if there is no writeback to the base register (LDM that loads into the base register) or the base register is killed by one of the merged instructions. These cases are clear wins both in terms of instruction count and performance. Also add three new test cases, and update the existing ones accordingly. llvm-svn: 215729
78 lines
2.5 KiB
LLVM
78 lines
2.5 KiB
LLVM
; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-cgp-branch-opts -disable-post-ra -verify-machineinstrs | FileCheck %s -check-prefix=CHECK
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; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-cgp-branch-opts -disable-post-ra -regalloc=basic -verify-machineinstrs | FileCheck %s -check-prefix=CHECK
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%struct.state = type { i32, %struct.info*, float**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i8* }
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%struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* }
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define void @t1(%struct.state* %v) {
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; CHECK-LABEL: t1:
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; CHECK: push
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; CHECK: add r7, sp, #12
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; CHECK: lsls r[[R0:[0-9]+]]
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; CHECK: mov r[[R1:[0-9]+]], sp
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; CHECK: subs r[[R2:[0-9]+]], r[[R1]], r[[R0]]
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; CHECK: mov sp, r[[R2]]
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%tmp6 = load i32* null
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%tmp8 = alloca float, i32 %tmp6
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store i32 1, i32* null
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br i1 false, label %bb123.preheader, label %return
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bb123.preheader:
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br i1 false, label %bb43, label %return
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bb43:
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call fastcc void @f1( float* %tmp8, float* null, i32 0 )
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%tmp70 = load i32* null
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%tmp85 = getelementptr float* %tmp8, i32 0
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call fastcc void @f2( float* null, float* null, float* %tmp85, i32 %tmp70 )
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ret void
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return:
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ret void
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}
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declare fastcc void @f1(float*, float*, i32)
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declare fastcc void @f2(float*, float*, float*, i32)
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%struct.comment = type { i8**, i32*, i32, i8* }
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@str215 = external global [2 x i8]
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define void @t2(%struct.comment* %vc, i8* %tag, i8* %contents) {
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; CHECK-LABEL: t2:
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; CHECK: push
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; CHECK: add r7, sp, #12
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; CHECK: sub sp, #
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; CHECK: mov r[[R0:[0-9]+]], sp
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; CHECK: str r{{[0-9+]}}, [r[[R0]]
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; CHECK: str r{{[0-9+]}}, [r[[R0]]
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; CHECK-NOT: ldr r0, [sp
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; CHECK: mov r[[R1:[0-9]+]], sp
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; CHECK: subs r[[R2:[0-9]+]], r[[R1]], r{{[0-9]+}}
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; CHECK: mov sp, r[[R2]]
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; CHECK-NOT: ldr r0, [sp
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; CHECK: bx
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%tmp1 = call i32 @strlen( i8* %tag )
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%tmp3 = call i32 @strlen( i8* %contents )
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%tmp4 = add i32 %tmp1, 2
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%tmp5 = add i32 %tmp4, %tmp3
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%tmp6 = alloca i8, i32 %tmp5
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%tmp9 = call i8* @strcpy( i8* %tmp6, i8* %tag )
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%tmp6.len = call i32 @strlen( i8* %tmp6 )
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%tmp6.indexed = getelementptr i8* %tmp6, i32 %tmp6.len
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call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp6.indexed, i8* getelementptr inbounds ([2 x i8]* @str215, i32 0, i32 0), i32 2, i32 1, i1 false)
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%tmp15 = call i8* @strcat( i8* %tmp6, i8* %contents )
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call fastcc void @comment_add( %struct.comment* %vc, i8* %tmp6 )
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ret void
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}
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declare i32 @strlen(i8*)
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declare i8* @strcat(i8*, i8*)
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declare fastcc void @comment_add(%struct.comment*, i8*)
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declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
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declare i8* @strcpy(i8*, i8*)
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