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llvm-mirror/test/CodeGen/Mips/micromips-atomic.ll
Aleksandar Beserminji 0c6deeab94 [mips] Fix atomic operations at O0, v3
Similar to PR/25526, fast-regalloc introduces spills at the end of basic
blocks. When this occurs in between an ll and sc, the stores can cause the
atomic sequence to fail.

This patch fixes the issue by introducing more pseudos to represent atomic
operations and moving their lowering to after the expansion of postRA
pseudos.

This version addresses issues with the initial implementation and covers
all atomic operations.

This resolves PR/32020.

Thanks to James Cowgill for reporting the issue!

Patch By: Simon Dardis

Differential Revision: https://reviews.llvm.org/D31287

llvm-svn: 336328
2018-07-05 09:27:05 +00:00

26 lines
872 B
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc %s -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r2 -mattr=micromips -filetype=asm \
; RUN: -relocation-model=pic -o - | FileCheck %s
@x = common global i32 0, align 4
define i32 @AtomicLoadAdd32(i32 %incr) nounwind {
; CHECK-LABEL: AtomicLoadAdd32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui $2, %hi(_gp_disp)
; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)
; CHECK-NEXT: addu $2, $2, $25
; CHECK-NEXT: lw $1, %got(x)($2)
; CHECK-NEXT: $BB0_1: # %entry
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ll $2, 0($1)
; CHECK-NEXT: addu16 $3, $2, $4
; CHECK-NEXT: sc $3, 0($1)
; CHECK-NEXT: beqzc $3, $BB0_1
; CHECK-NEXT: # %bb.2: # %entry
; CHECK-NEXT: jrc $ra
entry:
%0 = atomicrmw add i32* @x, i32 %incr monotonic
ret i32 %0
}