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c5866724c9
This should match the existing behaviour for passing complicated struct and array types, in particular HFAs come through like that from Clang. For C & C++ we still need to somehow support all the weird ABI flags, or at least those that are present in the IR (signext, byval, ...), and stack-based parameter passing. llvm-svn: 281977
268 lines
9.9 KiB
C++
268 lines
9.9 KiB
C++
//===-- llvm/lib/Target/AArch64/AArch64CallLowering.cpp - Call lowering ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements the lowering of LLVM calls to machine code calls for
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/// GlobalISel.
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///
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//===----------------------------------------------------------------------===//
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#include "AArch64CallLowering.h"
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#include "AArch64ISelLowering.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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#ifndef LLVM_BUILD_GLOBAL_ISEL
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#error "This shouldn't be built without GISel"
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#endif
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AArch64CallLowering::AArch64CallLowering(const AArch64TargetLowering &TLI)
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: CallLowering(&TLI) {
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}
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bool AArch64CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder,
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CCAssignFn *AssignFn,
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ArrayRef<Type *> ArgTypes,
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ArrayRef<unsigned> ArgRegs,
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AssignFnTy AssignValToReg) const {
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = *MF.getFunction();
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
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unsigned NumArgs = ArgTypes.size();
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auto CurTy = ArgTypes.begin();
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for (unsigned i = 0; i != NumArgs; ++i, ++CurTy) {
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MVT CurVT = MVT::getVT(*CurTy);
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if (AssignFn(i, CurVT, CurVT, CCValAssign::Full, ISD::ArgFlagsTy(), CCInfo))
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return false;
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}
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assert(ArgLocs.size() == ArgTypes.size() &&
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"We have a different number of location and args?!");
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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// FIXME: Support non-register argument.
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if (!VA.isRegLoc())
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return false;
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switch (VA.getLocInfo()) {
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default:
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// Unknown loc info!
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return false;
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case CCValAssign::Full:
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break;
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case CCValAssign::BCvt:
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// We don't care about bitcast.
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break;
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case CCValAssign::AExt:
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// Existing high bits are fine for anyext (whatever they are).
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break;
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case CCValAssign::SExt:
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case CCValAssign::ZExt:
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// Zero/Sign extend the register.
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// FIXME: Not yet implemented
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return false;
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}
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// Everything checks out, tell the caller where we've decided this
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// parameter/return value should go.
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AssignValToReg(MIRBuilder, ArgTypes[i], ArgRegs[i], VA.getLocReg());
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}
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return true;
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}
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void AArch64CallLowering::splitToValueTypes(
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unsigned Reg, Type *Ty, SmallVectorImpl<unsigned> &SplitRegs,
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SmallVectorImpl<Type *> &SplitTys, const DataLayout &DL,
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MachineRegisterInfo &MRI, SplitArgTy SplitArg) const {
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const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
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LLVMContext &Ctx = Ty->getContext();
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SmallVector<EVT, 4> SplitVTs;
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SmallVector<uint64_t, 4> Offsets;
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ComputeValueVTs(TLI, DL, Ty, SplitVTs, &Offsets, 0);
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if (SplitVTs.size() == 1) {
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// No splitting to do, just forward the input directly.
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SplitTys.push_back(Ty);
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SplitRegs.push_back(Reg);
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return;
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}
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unsigned FirstRegIdx = SplitRegs.size();
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for (auto SplitVT : SplitVTs) {
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Type *SplitTy = SplitVT.getTypeForEVT(Ctx);
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SplitRegs.push_back(MRI.createGenericVirtualRegister(LLT{*SplitTy, DL}));
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SplitTys.push_back(SplitTy);
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}
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SmallVector<uint64_t, 4> BitOffsets;
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for (auto Offset : Offsets)
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BitOffsets.push_back(Offset * 8);
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SplitArg(ArrayRef<unsigned>(&SplitRegs[FirstRegIdx], SplitRegs.end()),
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BitOffsets);
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}
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bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
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const Value *Val, unsigned VReg) const {
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = *MF.getFunction();
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MachineInstrBuilder MIB = MIRBuilder.buildInstr(AArch64::RET_ReallyLR);
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assert(MIB.getInstr() && "Unable to build a return instruction?!");
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assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg");
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if (VReg) {
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MIRBuilder.setInstr(*MIB.getInstr(), /* Before */ true);
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const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
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CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
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MachineRegisterInfo &MRI = MF.getRegInfo();
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auto &DL = F.getParent()->getDataLayout();
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SmallVector<Type *, 8> SplitTys;
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SmallVector<unsigned, 8> SplitRegs;
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splitToValueTypes(VReg, Val->getType(), SplitRegs, SplitTys, DL, MRI,
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[&](ArrayRef<unsigned> Regs, ArrayRef<uint64_t> Offsets) {
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MIRBuilder.buildExtract(Regs, Offsets, VReg);
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});
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return handleAssignments(MIRBuilder, AssignFn, SplitTys, SplitRegs,
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[&](MachineIRBuilder &MIRBuilder, Type *Ty,
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unsigned ValReg, unsigned PhysReg) {
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MIRBuilder.buildCopy(PhysReg, ValReg);
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MIB.addUse(PhysReg, RegState::Implicit);
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});
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}
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return true;
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}
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bool AArch64CallLowering::lowerFormalArguments(
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MachineIRBuilder &MIRBuilder, const Function::ArgumentListType &Args,
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ArrayRef<unsigned> VRegs) const {
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MachineFunction &MF = MIRBuilder.getMF();
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MachineBasicBlock &MBB = MIRBuilder.getMBB();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const Function &F = *MF.getFunction();
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auto &DL = F.getParent()->getDataLayout();
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SmallVector<MachineInstr *, 8> Seqs;
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SmallVector<Type *, 8> SplitTys;
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SmallVector<unsigned, 8> SplitRegs;
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unsigned i = 0;
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for (auto &Arg : Args) {
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splitToValueTypes(VRegs[i], Arg.getType(), SplitRegs, SplitTys, DL, MRI,
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[&](ArrayRef<unsigned> Regs, ArrayRef<uint64_t> Offsets) {
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MIRBuilder.buildSequence(VRegs[i], Regs, Offsets);
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});
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++i;
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}
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if (!MBB.empty())
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MIRBuilder.setInstr(*MBB.begin());
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const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
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CCAssignFn *AssignFn =
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TLI.CCAssignFnForCall(F.getCallingConv(), /*IsVarArg=*/false);
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bool Res = handleAssignments(MIRBuilder, AssignFn, SplitTys, SplitRegs,
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[](MachineIRBuilder &MIRBuilder, Type *Ty,
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unsigned ValReg, unsigned PhysReg) {
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MIRBuilder.getMBB().addLiveIn(PhysReg);
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MIRBuilder.buildCopy(ValReg, PhysReg);
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});
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// Move back to the end of the basic block.
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MIRBuilder.setMBB(MBB);
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return Res;
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}
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bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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const MachineOperand &Callee, Type *ResTy,
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unsigned ResReg, ArrayRef<Type *> ArgTys,
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ArrayRef<unsigned> ArgRegs) const {
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = *MF.getFunction();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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auto &DL = F.getParent()->getDataLayout();
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SmallVector<Type *, 8> SplitTys;
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SmallVector<unsigned, 8> SplitRegs;
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for (unsigned i = 0; i < ArgTys.size(); ++i) {
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splitToValueTypes(ArgRegs[i], ArgTys[i], SplitRegs, SplitTys, DL, MRI,
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[&](ArrayRef<unsigned> Regs, ArrayRef<uint64_t> Offsets) {
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MIRBuilder.buildExtract(Regs, Offsets, ArgRegs[i]);
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});
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}
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// Find out which ABI gets to decide where things go.
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const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
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CCAssignFn *CallAssignFn =
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TLI.CCAssignFnForCall(F.getCallingConv(), /*IsVarArg=*/false);
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// And finally we can do the actual assignments. For a call we need to keep
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// track of the registers used because they'll be implicit uses of the BL.
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SmallVector<unsigned, 8> PhysRegs;
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handleAssignments(MIRBuilder, CallAssignFn, SplitTys, SplitRegs,
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[&](MachineIRBuilder &MIRBuilder, Type *Ty, unsigned ValReg,
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unsigned PhysReg) {
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MIRBuilder.buildCopy(PhysReg, ValReg);
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PhysRegs.push_back(PhysReg);
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});
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// Now we can build the actual call instruction.
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auto MIB = MIRBuilder.buildInstr(Callee.isReg() ? AArch64::BLR : AArch64::BL);
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MIB.addOperand(Callee);
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// Tell the call which registers are clobbered.
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auto TRI = MF.getSubtarget().getRegisterInfo();
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MIB.addRegMask(TRI->getCallPreservedMask(MF, F.getCallingConv()));
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for (auto Reg : PhysRegs)
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MIB.addUse(Reg, RegState::Implicit);
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// Finally we can copy the returned value back into its virtual-register. In
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// symmetry with the arugments, the physical register must be an
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// implicit-define of the call instruction.
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CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
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if (ResReg) {
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SplitTys.clear();
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SplitRegs.clear();
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SmallVector<uint64_t, 8> RegOffsets;
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splitToValueTypes(ResReg, ResTy, SplitRegs, SplitTys, DL, MRI,
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[&](ArrayRef<unsigned> Regs, ArrayRef<uint64_t> Offsets) {
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std::copy(Offsets.begin(), Offsets.end(),
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std::back_inserter(RegOffsets));
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});
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handleAssignments(MIRBuilder, RetAssignFn, SplitTys, SplitRegs,
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[&](MachineIRBuilder &MIRBuilder, Type *Ty,
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unsigned ValReg, unsigned PhysReg) {
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MIRBuilder.buildCopy(ValReg, PhysReg);
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MIB.addDef(PhysReg, RegState::Implicit);
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});
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if (!RegOffsets.empty())
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MIRBuilder.buildSequence(ResReg, SplitRegs, RegOffsets);
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}
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return true;
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}
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