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251 lines
8.9 KiB
C++
251 lines
8.9 KiB
C++
//===- AArch64RegisterBankInfo.cpp -------------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the RegisterBankInfo class for
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/// AArch64.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "AArch64RegisterBankInfo.h"
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#include "AArch64InstrInfo.h" // For XXXRegClassID.
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#include "llvm/CodeGen/LowLevelType.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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#ifndef LLVM_BUILD_GLOBAL_ISEL
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#error "You shouldn't build this"
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#endif
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AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
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: RegisterBankInfo(AArch64::NumRegisterBanks) {
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// Initialize the GPR bank.
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createRegisterBank(AArch64::GPRRegBankID, "GPR");
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// The GPR register bank is fully defined by all the registers in
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// GR64all + its subclasses.
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addRegBankCoverage(AArch64::GPRRegBankID, AArch64::GPR64allRegClassID, TRI);
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const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
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(void)RBGPR;
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assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
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"Subclass not added?");
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assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit");
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// Initialize the FPR bank.
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createRegisterBank(AArch64::FPRRegBankID, "FPR");
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// The FPR register bank is fully defined by all the registers in
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// GR64all + its subclasses.
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addRegBankCoverage(AArch64::FPRRegBankID, AArch64::QQQQRegClassID, TRI);
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const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
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(void)RBFPR;
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assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&
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"Subclass not added?");
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assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&
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"Subclass not added?");
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assert(RBFPR.getSize() == 512 &&
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"FPRs should hold up to 512-bit via QQQQ sequence");
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// Initialize the CCR bank.
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createRegisterBank(AArch64::CCRRegBankID, "CCR");
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addRegBankCoverage(AArch64::CCRRegBankID, AArch64::CCRRegClassID, TRI);
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const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID);
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(void)RBCCR;
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assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
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"Class not added?");
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assert(RBCCR.getSize() == 32 && "CCR should hold up to 32-bit");
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assert(verify(TRI) && "Invalid register bank information");
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}
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unsigned AArch64RegisterBankInfo::copyCost(const RegisterBank &A,
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const RegisterBank &B,
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unsigned Size) const {
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// What do we do with different size?
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// copy are same size.
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// Will introduce other hooks for different size:
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// * extract cost.
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// * build_sequence cost.
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// TODO: Add more accurate cost for FPR to/from GPR.
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return RegisterBankInfo::copyCost(A, B, Size);
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}
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const RegisterBank &AArch64RegisterBankInfo::getRegBankFromRegClass(
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const TargetRegisterClass &RC) const {
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switch (RC.getID()) {
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case AArch64::FPR8RegClassID:
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case AArch64::FPR16RegClassID:
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case AArch64::FPR32RegClassID:
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case AArch64::FPR64RegClassID:
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case AArch64::FPR128RegClassID:
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case AArch64::FPR128_loRegClassID:
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case AArch64::DDRegClassID:
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case AArch64::DDDRegClassID:
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case AArch64::DDDDRegClassID:
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case AArch64::QQRegClassID:
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case AArch64::QQQRegClassID:
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case AArch64::QQQQRegClassID:
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return getRegBank(AArch64::FPRRegBankID);
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case AArch64::GPR32commonRegClassID:
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case AArch64::GPR32RegClassID:
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case AArch64::GPR32spRegClassID:
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case AArch64::GPR32sponlyRegClassID:
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case AArch64::GPR32allRegClassID:
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case AArch64::GPR64commonRegClassID:
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case AArch64::GPR64RegClassID:
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case AArch64::GPR64spRegClassID:
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case AArch64::GPR64sponlyRegClassID:
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case AArch64::GPR64allRegClassID:
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case AArch64::tcGPR64RegClassID:
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case AArch64::WSeqPairsClassRegClassID:
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case AArch64::XSeqPairsClassRegClassID:
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return getRegBank(AArch64::GPRRegBankID);
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case AArch64::CCRRegClassID:
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return getRegBank(AArch64::CCRRegBankID);
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default:
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llvm_unreachable("Register class not supported");
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}
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}
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RegisterBankInfo::InstructionMappings
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AArch64RegisterBankInfo::getInstrAlternativeMappings(
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const MachineInstr &MI) const {
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switch (MI.getOpcode()) {
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case TargetOpcode::G_OR: {
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// 32 and 64-bit or can be mapped on either FPR or
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// GPR for the same cost.
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const MachineFunction &MF = *MI.getParent()->getParent();
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const TargetSubtargetInfo &STI = MF.getSubtarget();
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const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
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if (Size != 32 && Size != 64)
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break;
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// If the instruction has any implicit-defs or uses,
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// do not mess with it.
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if (MI.getNumOperands() != 3)
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break;
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InstructionMappings AltMappings;
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InstructionMapping GPRMapping(/*ID*/ 1, /*Cost*/ 1, /*NumOperands*/ 3);
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InstructionMapping FPRMapping(/*ID*/ 2, /*Cost*/ 1, /*NumOperands*/ 3);
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for (unsigned Idx = 0; Idx != 3; ++Idx) {
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GPRMapping.setOperandMapping(Idx, Size,
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getRegBank(AArch64::GPRRegBankID));
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FPRMapping.setOperandMapping(Idx, Size,
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getRegBank(AArch64::FPRRegBankID));
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}
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AltMappings.emplace_back(std::move(GPRMapping));
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AltMappings.emplace_back(std::move(FPRMapping));
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return AltMappings;
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}
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default:
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break;
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}
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return RegisterBankInfo::getInstrAlternativeMappings(MI);
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}
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void AArch64RegisterBankInfo::applyMappingImpl(
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const OperandsMapper &OpdMapper) const {
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switch (OpdMapper.getMI().getOpcode()) {
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case TargetOpcode::G_OR: {
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// Those ID must match getInstrAlternativeMappings.
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assert((OpdMapper.getInstrMapping().getID() == 1 ||
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OpdMapper.getInstrMapping().getID() == 2) &&
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"Don't know how to handle that ID");
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return applyDefaultMapping(OpdMapper);
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}
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default:
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llvm_unreachable("Don't know how to handle that operation");
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}
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}
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/// Returns whether opcode \p Opc is a pre-isel generic floating-point opcode,
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/// having only floating-point operands.
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static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
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switch (Opc) {
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case TargetOpcode::G_FADD:
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case TargetOpcode::G_FSUB:
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case TargetOpcode::G_FMUL:
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case TargetOpcode::G_FDIV:
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case TargetOpcode::G_FCONSTANT:
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case TargetOpcode::G_FPEXT:
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case TargetOpcode::G_FPTRUNC:
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return true;
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}
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return false;
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}
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RegisterBankInfo::InstructionMapping
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AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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const unsigned Opc = MI.getOpcode();
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const MachineFunction &MF = *MI.getParent()->getParent();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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// Try the default logic for non-generic instructions that are either copies
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// or already have some operands assigned to banks.
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if (!isPreISelGenericOpcode(Opc)) {
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RegisterBankInfo::InstructionMapping Mapping = getInstrMappingImpl(MI);
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if (Mapping.isValid())
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return Mapping;
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}
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RegisterBankInfo::InstructionMapping Mapping =
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InstructionMapping{DefaultMappingID, 1, MI.getNumOperands()};
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// Track the size and bank of each register. We don't do partial mappings.
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SmallVector<unsigned, 4> OpSizes(MI.getNumOperands());
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SmallVector<unsigned, 4> OpBanks(MI.getNumOperands());
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for (unsigned Idx = 0; Idx < MI.getNumOperands(); ++Idx) {
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auto &MO = MI.getOperand(Idx);
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if (!MO.isReg())
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continue;
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LLT Ty = MRI.getType(MO.getReg());
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OpSizes[Idx] = Ty.getSizeInBits();
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// As a top-level guess, vectors go in FPRs, scalars and pointers in GPRs.
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// For floating-point instructions, scalars go in FPRs.
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if (Ty.isVector() || isPreISelGenericFloatingPointOpcode(Opc))
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OpBanks[Idx] = AArch64::FPRRegBankID;
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else
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OpBanks[Idx] = AArch64::GPRRegBankID;
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}
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// Some of the floating-point instructions have mixed GPR and FPR operands:
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// fine-tune the computed mapping.
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switch (Opc) {
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case TargetOpcode::G_SITOFP:
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case TargetOpcode::G_UITOFP: {
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OpBanks = {AArch64::FPRRegBankID, AArch64::GPRRegBankID};
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break;
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}
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case TargetOpcode::G_FPTOSI:
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case TargetOpcode::G_FPTOUI: {
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OpBanks = {AArch64::GPRRegBankID, AArch64::FPRRegBankID};
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break;
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}
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case TargetOpcode::G_FCMP: {
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OpBanks = {AArch64::GPRRegBankID, /* Predicate */ 0, AArch64::FPRRegBankID,
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AArch64::FPRRegBankID};
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break;
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}
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}
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// Finally construct the computed mapping.
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for (unsigned Idx = 0; Idx < MI.getNumOperands(); ++Idx)
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if (MI.getOperand(Idx).isReg())
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Mapping.setOperandMapping(Idx, OpSizes[Idx], getRegBank(OpBanks[Idx]));
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return Mapping;
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}
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