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d815d3c37a
Having a custom inliner doesn't really fit in with the new PM's pipeline. It's also extra technical debt. amdgpu-inline only does a couple of custom things compared to the normal inliner: 1) It disables inlining if the number of BBs in a function would exceed some limit 2) It increases the threshold if there are pointers to private arrays(?) These can all be handled as TTI inliner hooks. There already exists a hook for backends to multiply the inlining threshold. This way we can remove the custom amdgpu-inline pass. This caused inline-hint.ll to fail, and after some investigation, it looks like getInliningThresholdMultiplier() was previously getting applied twice in amdgpu-inline (https://reviews.llvm.org/D62707 fixed it not applying at all, so some later inliner change must have fixed something), so I had to change the threshold in the test. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D94153
71 lines
1.7 KiB
LLVM
71 lines
1.7 KiB
LLVM
; RUN: opt -mtriple=amdgcn-- -inline -S -amdgpu-inline-max-bb=2 %s | FileCheck %s --check-prefix=NOINL
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; RUN: opt -mtriple=amdgcn-- -inline -S -amdgpu-inline-max-bb=3 %s | FileCheck %s --check-prefix=INL
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; RUN: opt -mtriple=amdgcn-- -passes=inline -S -amdgpu-inline-max-bb=2 %s | FileCheck %s --check-prefix=NOINL
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; RUN: opt -mtriple=amdgcn-- -passes=inline -S -amdgpu-inline-max-bb=3 %s | FileCheck %s --check-prefix=INL
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define i32 @callee(i32 %x) {
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entry:
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%cc = icmp eq i32 %x, 1
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br i1 %cc, label %ret_res, label %mulx
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mulx:
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%mul1 = mul i32 %x, %x
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%mul2 = mul i32 %mul1, %x
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%mul3 = mul i32 %mul1, %mul2
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%mul4 = mul i32 %mul3, %mul2
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%mul5 = mul i32 %mul4, %mul3
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br label %ret_res
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ret_res:
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%r = phi i32 [ %mul5, %mulx ], [ %x, %entry ]
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ret i32 %r
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}
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; INL-LABEL: @caller
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; NOINL-LABEL: @caller
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; INL: mul i32
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; INL-NOT: call i32
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; NOINL-NOT: mul i32
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; NOINL: call i32
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define amdgpu_kernel void @caller(i32 %x) {
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%res = call i32 @callee(i32 %x)
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store volatile i32 %res, i32 addrspace(1)* undef
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ret void
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}
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; inlinehint
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define i32 @callee_hint(i32 %x) #0 {
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entry:
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%cc = icmp eq i32 %x, 1
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br i1 %cc, label %ret_res, label %mulx
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mulx:
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%mul1 = mul i32 %x, %x
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%mul2 = mul i32 %mul1, %x
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%mul3 = mul i32 %mul1, %mul2
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%mul4 = mul i32 %mul3, %mul2
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%mul5 = mul i32 %mul4, %mul3
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br label %ret_res
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ret_res:
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%r = phi i32 [ %mul5, %mulx ], [ %x, %entry ]
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ret i32 %r
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}
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; INL-LABEL: @caller_hint
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; NOINL-LABEL: @caller_hint
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; INL: mul i32
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; INL-NOT: call i32
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; NOINL: mul i32
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; NOINL-NOT: call i32
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define amdgpu_kernel void @caller_hint(i32 %x) {
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%res = call i32 @callee_hint(i32 %x)
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store volatile i32 %res, i32 addrspace(1)* undef
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ret void
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}
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attributes #0 = { inlinehint }
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