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https://github.com/RPCS3/llvm-mirror.git
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3f23d4b8c3
tryLatency compares two sched candidates. For the top zone it prefers the one with lesser depth, but only if that depth is greater than the total latency of the instructions we've already scheduled -- otherwise its latency would be hidden and there would be no stall. Unfortunately it only tests the depth of one of the candidates. This can lead to situations where the TopDepthReduce heuristic does not kick in, but a lower priority heuristic chooses the other candidate, whose depth *is* greater than the already scheduled latency, which causes a stall. The fix is to apply the heuristic if the depth of *either* candidate is greater than the already scheduled latency. All this also applies to the BotHeightReduce heuristic in the bottom zone. Differential Revision: https://reviews.llvm.org/D72392
210 lines
12 KiB
LLVM
210 lines
12 KiB
LLVM
;RUN: llc < %s -march=amdgcn -mcpu=verde -amdgpu-atomic-optimizations=false -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI
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;RUN: llc < %s -march=amdgcn -mcpu=tonga -amdgpu-atomic-optimizations=false -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI
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;CHECK-LABEL: {{^}}test1:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_atomic_swap v0, off, s[0:3], 0 glc
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;VI: s_movk_i32 [[SOFS:s[0-9]+]], 0x1ffc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_swap v0, v1, s[0:3], 0 idxen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_swap v0, v2, s[0:3], 0 offen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_swap v0, v[1:2], s[0:3], 0 idxen offen glc
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;SICI: v_mov_b32_e32 v1, 0x2000
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_swap v0, v2, s[0:3], 0 offen offset:42 glc
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;CHECK-DAG: s_waitcnt vmcnt(0)
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;SICI: buffer_atomic_swap v0, v1, s[0:3], 0 offen glc
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;VI: buffer_atomic_swap v0, off, s[0:3], [[SOFS]] offset:4 glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_swap v0, off, s[0:3], 0{{$}}
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define amdgpu_ps float @test1(<4 x i32> inreg %rsrc, i32 %data, i32 %vindex, i32 %voffset) {
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main_body:
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%o1 = call i32 @llvm.amdgcn.buffer.atomic.swap.i32(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
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%o2 = call i32 @llvm.amdgcn.buffer.atomic.swap.i32(i32 %o1, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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%o3 = call i32 @llvm.amdgcn.buffer.atomic.swap.i32(i32 %o2, <4 x i32> %rsrc, i32 0, i32 %voffset, i1 0)
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%o4 = call i32 @llvm.amdgcn.buffer.atomic.swap.i32(i32 %o3, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i1 0)
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%ofs.5 = add i32 %voffset, 42
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%o5 = call i32 @llvm.amdgcn.buffer.atomic.swap.i32(i32 %o4, <4 x i32> %rsrc, i32 0, i32 %ofs.5, i1 0)
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%o6 = call i32 @llvm.amdgcn.buffer.atomic.swap.i32(i32 %o5, <4 x i32> %rsrc, i32 0, i32 8192, i1 0)
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%unused = call i32 @llvm.amdgcn.buffer.atomic.swap.i32(i32 %o6, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
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%out = bitcast i32 %o6 to float
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ret float %out
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}
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;CHECK-LABEL: {{^}}test11:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_atomic_swap_x2 v[3:4], off, s[0:3], 0 glc
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;VI: s_movk_i32 [[SOFS:s[0-9]+]], 0x1ffc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_swap_x2 v[3:4], v1, s[0:3], 0 idxen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_swap_x2 v[3:4], v2, s[0:3], 0 offen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_swap_x2 v[3:4], v[1:2], s[0:3], 0 idxen offen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_swap_x2 v[3:4], v2, s[0:3], 0 offen offset:42 glc
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;CHECK-DAG: s_waitcnt vmcnt(0)
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;SICI: buffer_atomic_swap_x2 v[3:4], v0, s[0:3], 0 offen glc
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;VI: buffer_atomic_swap_x2 v[3:4], off, s[0:3], [[SOFS]] offset:4 glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_swap_x2 v[3:4], off, s[0:3], 0{{$}}
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define amdgpu_ps float @test11(<4 x i32> inreg %rsrc, i32 %data, i32 %vindex, i32 %voffset) {
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main_body:
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%o0 = sext i32 %data to i64
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%o1 = call i64 @llvm.amdgcn.buffer.atomic.swap.i64(i64 %o0, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
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%o2 = call i64 @llvm.amdgcn.buffer.atomic.swap.i64(i64 %o1, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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%o3 = call i64 @llvm.amdgcn.buffer.atomic.swap.i64(i64 %o2, <4 x i32> %rsrc, i32 0, i32 %voffset, i1 0)
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%o4 = call i64 @llvm.amdgcn.buffer.atomic.swap.i64(i64 %o3, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i1 0)
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%ofs.5 = add i32 %voffset, 42
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%o5 = call i64 @llvm.amdgcn.buffer.atomic.swap.i64(i64 %o4, <4 x i32> %rsrc, i32 0, i32 %ofs.5, i1 0)
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%o6 = call i64 @llvm.amdgcn.buffer.atomic.swap.i64(i64 %o5, <4 x i32> %rsrc, i32 0, i32 8192, i1 0)
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%unused = call i64 @llvm.amdgcn.buffer.atomic.swap.i64(i64 %o6, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
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%o7 = trunc i64 %o6 to i32
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%out = bitcast i32 %o7 to float
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ret float %out
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}
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;CHECK-LABEL: {{^}}test2:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_atomic_add v0, v1, s[0:3], 0 idxen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_sub v0, v1, s[0:3], 0 idxen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_smin v0, v1, s[0:3], 0 idxen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_umin v0, v1, s[0:3], 0 idxen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_smax v0, v1, s[0:3], 0 idxen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_umax v0, v1, s[0:3], 0 idxen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_and v0, v1, s[0:3], 0 idxen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_or v0, v1, s[0:3], 0 idxen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_xor v0, v1, s[0:3], 0 idxen glc
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define amdgpu_ps float @test2(<4 x i32> inreg %rsrc, i32 %data, i32 %vindex) {
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main_body:
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%t1 = call i32 @llvm.amdgcn.buffer.atomic.add.i32(i32 %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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%t2 = call i32 @llvm.amdgcn.buffer.atomic.sub.i32(i32 %t1, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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%t3 = call i32 @llvm.amdgcn.buffer.atomic.smin.i32(i32 %t2, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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%t4 = call i32 @llvm.amdgcn.buffer.atomic.umin.i32(i32 %t3, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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%t5 = call i32 @llvm.amdgcn.buffer.atomic.smax.i32(i32 %t4, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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%t6 = call i32 @llvm.amdgcn.buffer.atomic.umax.i32(i32 %t5, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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%t7 = call i32 @llvm.amdgcn.buffer.atomic.and.i32(i32 %t6, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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%t8 = call i32 @llvm.amdgcn.buffer.atomic.or.i32(i32 %t7, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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%t9 = call i32 @llvm.amdgcn.buffer.atomic.xor.i32(i32 %t8, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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%out = bitcast i32 %t9 to float
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ret float %out
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}
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;CHECK-LABEL: {{^}}test3:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_atomic_add_x2 v[0:1], v2, s[0:3], 0 idxen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_sub_x2 v[0:1], v2, s[0:3], 0 idxen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_smin_x2 v[0:1], v2, s[0:3], 0 idxen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_umin_x2 v[0:1], v2, s[0:3], 0 idxen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_smax_x2 v[0:1], v2, s[0:3], 0 idxen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_umax_x2 v[0:1], v2, s[0:3], 0 idxen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_and_x2 v[0:1], v2, s[0:3], 0 idxen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_or_x2 v[0:1], v2, s[0:3], 0 idxen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_xor_x2 v[0:1], v2, s[0:3], 0 idxen glc
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define amdgpu_ps float @test3(<4 x i32> inreg %rsrc, i32 %data, i32 %vindex) {
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main_body:
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%t0 = sext i32 %data to i64
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%t1 = call i64 @llvm.amdgcn.buffer.atomic.add.i64(i64 %t0, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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%t2 = call i64 @llvm.amdgcn.buffer.atomic.sub.i64(i64 %t1, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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%t3 = call i64 @llvm.amdgcn.buffer.atomic.smin.i64(i64 %t2, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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%t4 = call i64 @llvm.amdgcn.buffer.atomic.umin.i64(i64 %t3, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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%t5 = call i64 @llvm.amdgcn.buffer.atomic.smax.i64(i64 %t4, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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%t6 = call i64 @llvm.amdgcn.buffer.atomic.umax.i64(i64 %t5, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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%t7 = call i64 @llvm.amdgcn.buffer.atomic.and.i64(i64 %t6, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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%t8 = call i64 @llvm.amdgcn.buffer.atomic.or.i64(i64 %t7, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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%t9 = call i64 @llvm.amdgcn.buffer.atomic.xor.i64(i64 %t8, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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%t10 = trunc i64 %t9 to i32
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%out = bitcast i32 %t10 to float
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ret float %out
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}
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; Ideally, we would teach tablegen & friends that cmpswap only modifies the
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; first vgpr. Since we don't do that yet, the register allocator will have to
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; create copies which we don't bother to track here.
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;
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;CHECK-LABEL: {{^}}test4:
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;CHECK-NOT: s_waitcnt
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;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], 0 glc
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;CHECK: s_waitcnt vmcnt(0)
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;VI: s_movk_i32 [[SOFS:s[0-9]+]], 0x1ffc
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;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v2, s[0:3], 0 idxen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v3, s[0:3], 0 offen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v[2:3], s[0:3], 0 idxen offen glc
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;CHECK: s_waitcnt vmcnt(0)
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;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v3, s[0:3], 0 offen offset:44 glc
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;CHECK-DAG: s_waitcnt vmcnt(0)
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;SICI: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, s[0:3], 0 offen glc
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;VI: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], [[SOFS]] offset:4 glc
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define amdgpu_ps float @test4(<4 x i32> inreg %rsrc, i32 %data, i32 %cmp, i32 %vindex, i32 %voffset) {
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main_body:
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%o1 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %data, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
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%o2 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o1, i32 %cmp, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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%o3 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o2, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 %voffset, i1 0)
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%o4 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o3, i32 %cmp, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i1 0)
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%ofs.5 = add i32 %voffset, 44
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%o5 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o4, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 %ofs.5, i1 0)
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%o6 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o5, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 8192, i1 0)
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; Detecting the no-return variant doesn't work right now because of how the
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; intrinsic is replaced by an instruction that feeds into an EXTRACT_SUBREG.
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; Since there probably isn't a reasonable use-case of cmpswap that discards
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; the return value, that seems okay.
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;
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; %unused = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o6, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
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%out = bitcast i32 %o6 to float
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ret float %out
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}
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;CHECK-LABEL: {{^}}test7:
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;CHECK: buffer_atomic_add v0,
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define amdgpu_ps float @test7() {
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main_body:
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%v = call i32 @llvm.amdgcn.buffer.atomic.add.i32(i32 1, <4 x i32> undef, i32 0, i32 4, i1 false)
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%v.float = bitcast i32 %v to float
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ret float %v.float
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}
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declare i32 @llvm.amdgcn.buffer.atomic.swap.i32(i32, <4 x i32>, i32, i32, i1) #0
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declare i32 @llvm.amdgcn.buffer.atomic.add.i32(i32, <4 x i32>, i32, i32, i1) #0
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declare i32 @llvm.amdgcn.buffer.atomic.sub.i32(i32, <4 x i32>, i32, i32, i1) #0
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declare i32 @llvm.amdgcn.buffer.atomic.smin.i32(i32, <4 x i32>, i32, i32, i1) #0
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declare i32 @llvm.amdgcn.buffer.atomic.umin.i32(i32, <4 x i32>, i32, i32, i1) #0
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declare i32 @llvm.amdgcn.buffer.atomic.smax.i32(i32, <4 x i32>, i32, i32, i1) #0
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declare i32 @llvm.amdgcn.buffer.atomic.umax.i32(i32, <4 x i32>, i32, i32, i1) #0
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declare i32 @llvm.amdgcn.buffer.atomic.and.i32(i32, <4 x i32>, i32, i32, i1) #0
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declare i32 @llvm.amdgcn.buffer.atomic.or.i32(i32, <4 x i32>, i32, i32, i1) #0
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declare i32 @llvm.amdgcn.buffer.atomic.xor.i32(i32, <4 x i32>, i32, i32, i1) #0
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declare i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32, i32, <4 x i32>, i32, i32, i1) #0
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declare i64 @llvm.amdgcn.buffer.atomic.swap.i64(i64, <4 x i32>, i32, i32, i1) #0
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declare i64 @llvm.amdgcn.buffer.atomic.add.i64(i64, <4 x i32>, i32, i32, i1) #0
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declare i64 @llvm.amdgcn.buffer.atomic.sub.i64(i64, <4 x i32>, i32, i32, i1) #0
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declare i64 @llvm.amdgcn.buffer.atomic.smin.i64(i64, <4 x i32>, i32, i32, i1) #0
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declare i64 @llvm.amdgcn.buffer.atomic.umin.i64(i64, <4 x i32>, i32, i32, i1) #0
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declare i64 @llvm.amdgcn.buffer.atomic.smax.i64(i64, <4 x i32>, i32, i32, i1) #0
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declare i64 @llvm.amdgcn.buffer.atomic.umax.i64(i64, <4 x i32>, i32, i32, i1) #0
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declare i64 @llvm.amdgcn.buffer.atomic.and.i64(i64, <4 x i32>, i32, i32, i1) #0
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declare i64 @llvm.amdgcn.buffer.atomic.or.i64(i64, <4 x i32>, i32, i32, i1) #0
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declare i64 @llvm.amdgcn.buffer.atomic.xor.i64(i64, <4 x i32>, i32, i32, i1) #0
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attributes #0 = { nounwind }
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