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ab043ff680
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
114 lines
6.6 KiB
LLVM
114 lines
6.6 KiB
LLVM
; RUN: llc -mtriple=armv7-eabi -mcpu=cortex-a8 < %s
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; PR5412
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; rdar://7384107
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%bar = type { %quad, float, float, [3 x %quuz*], [3 x %bar*], [2 x %bar*], [3 x i8], i8 }
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%baz = type { %bar*, i32 }
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%foo = type { i8, %quux, %quad, float, [64 x %quuz], [128 x %bar], i32, %baz, %baz }
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%quad = type { [4 x float] }
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%quux = type { [4 x %quuz*], [4 x float], i32 }
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%quuz = type { %quad, %quad }
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define arm_aapcs_vfpcc %bar* @aaa(%foo* nocapture %this, %quuz* %a, %quuz* %b, %quuz* %c, i8 zeroext %forced) {
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entry:
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%0 = load %bar*, %bar** undef, align 4 ; <%bar*> [#uses=2]
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br i1 false, label %bb85, label %bb
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bb: ; preds = %entry
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br i1 undef, label %bb3.i, label %bb2.i
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bb2.i: ; preds = %bb
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br label %bb3.i
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bb3.i: ; preds = %bb2.i, %bb
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%1 = getelementptr inbounds %quuz, %quuz* %a, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=1]
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%2 = fsub float 0.000000e+00, undef ; <float> [#uses=1]
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%3 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1]
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%4 = getelementptr inbounds %quuz, %quuz* %b, i32 0, i32 1, i32 0, i32 2 ; <float*> [#uses=1]
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%5 = fsub float 0.000000e+00, undef ; <float> [#uses=1]
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%6 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 0 ; <float*> [#uses=1]
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%7 = getelementptr inbounds %quuz, %quuz* %c, i32 0, i32 1, i32 0, i32 1 ; <float*> [#uses=1]
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%8 = fsub float undef, undef ; <float> [#uses=1]
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%9 = fmul float 0.000000e+00, %8 ; <float> [#uses=1]
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%10 = fmul float %5, 0.000000e+00 ; <float> [#uses=1]
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%11 = fsub float %9, %10 ; <float> [#uses=3]
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%12 = fmul float %2, 0.000000e+00 ; <float> [#uses=1]
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%13 = fmul float 0.000000e+00, undef ; <float> [#uses=1]
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%14 = fsub float %12, %13 ; <float> [#uses=2]
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store float %14, float* undef
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%15 = getelementptr inbounds %bar, %bar* %0, i32 0, i32 0, i32 0, i32 3 ; <float*> [#uses=1]
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store float 0.000000e+00, float* %15
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%16 = fmul float %11, %11 ; <float> [#uses=1]
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%17 = fadd float %16, 0.000000e+00 ; <float> [#uses=1]
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%18 = fadd float %17, undef ; <float> [#uses=1]
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%19 = call arm_aapcs_vfpcc float @sqrtf(float %18) readnone ; <float> [#uses=2]
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%20 = fcmp ogt float %19, 0x3F1A36E2E0000000 ; <i1> [#uses=1]
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%21 = load float, float* %1, align 4 ; <float> [#uses=2]
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%22 = load float, float* %3, align 4 ; <float> [#uses=2]
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%23 = load float, float* undef, align 4 ; <float> [#uses=2]
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%24 = load float, float* %4, align 4 ; <float> [#uses=2]
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%25 = fsub float %23, %24 ; <float> [#uses=2]
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%26 = fmul float 0.000000e+00, %25 ; <float> [#uses=1]
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%27 = fsub float %26, undef ; <float> [#uses=1]
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%28 = fmul float %14, 0.000000e+00 ; <float> [#uses=1]
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%29 = fmul float %11, %25 ; <float> [#uses=1]
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%30 = fsub float %28, %29 ; <float> [#uses=1]
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%31 = fsub float undef, 0.000000e+00 ; <float> [#uses=1]
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%32 = fmul float %21, %27 ; <float> [#uses=1]
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%33 = fmul float undef, %30 ; <float> [#uses=1]
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%34 = fadd float %32, %33 ; <float> [#uses=1]
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%35 = fmul float %23, %31 ; <float> [#uses=1]
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%36 = fadd float %34, %35 ; <float> [#uses=1]
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%37 = load float, float* %6, align 4 ; <float> [#uses=2]
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%38 = load float, float* %7, align 4 ; <float> [#uses=2]
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%39 = fsub float %22, %38 ; <float> [#uses=2]
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%40 = load float, float* undef, align 4 ; <float> [#uses=1]
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%41 = load float, float* null, align 4 ; <float> [#uses=2]
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%42 = fmul float %41, undef ; <float> [#uses=1]
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%43 = fmul float undef, %39 ; <float> [#uses=1]
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%44 = fsub float %42, %43 ; <float> [#uses=1]
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%45 = fmul float undef, %39 ; <float> [#uses=1]
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%46 = fmul float %41, 0.000000e+00 ; <float> [#uses=1]
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%47 = fsub float %45, %46 ; <float> [#uses=1]
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%48 = fmul float 0.000000e+00, %44 ; <float> [#uses=1]
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%49 = fmul float %22, undef ; <float> [#uses=1]
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%50 = fadd float %48, %49 ; <float> [#uses=1]
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%51 = fmul float %24, %47 ; <float> [#uses=1]
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%52 = fadd float %50, %51 ; <float> [#uses=1]
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%53 = fsub float %37, %21 ; <float> [#uses=2]
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%54 = fmul float undef, undef ; <float> [#uses=1]
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%55 = fmul float undef, undef ; <float> [#uses=1]
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%56 = fsub float %54, %55 ; <float> [#uses=1]
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%57 = fmul float undef, %53 ; <float> [#uses=1]
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%58 = load float, float* undef, align 4 ; <float> [#uses=2]
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%59 = fmul float %58, undef ; <float> [#uses=1]
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%60 = fsub float %57, %59 ; <float> [#uses=1]
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%61 = fmul float %58, undef ; <float> [#uses=1]
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%62 = fmul float undef, %53 ; <float> [#uses=1]
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%63 = fsub float %61, %62 ; <float> [#uses=1]
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%64 = fmul float %37, %56 ; <float> [#uses=1]
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%65 = fmul float %38, %60 ; <float> [#uses=1]
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%66 = fadd float %64, %65 ; <float> [#uses=1]
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%67 = fmul float %40, %63 ; <float> [#uses=1]
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%68 = fadd float %66, %67 ; <float> [#uses=1]
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%69 = select i1 undef, float %36, float %52 ; <float> [#uses=1]
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%70 = select i1 undef, float %69, float %68 ; <float> [#uses=1]
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%iftmp.164.0 = select i1 %20, float %19, float 1.000000e+00 ; <float> [#uses=1]
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%71 = fdiv float %70, %iftmp.164.0 ; <float> [#uses=1]
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store float %71, float* null, align 4
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%72 = icmp eq %bar* null, %0 ; <i1> [#uses=1]
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br i1 %72, label %bb4.i97, label %ccc.exit98
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bb4.i97: ; preds = %bb3.i
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%73 = load %bar*, %bar** undef, align 4 ; <%bar*> [#uses=0]
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br label %ccc.exit98
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ccc.exit98: ; preds = %bb4.i97, %bb3.i
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ret %bar* null
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bb85: ; preds = %entry
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ret %bar* null
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}
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declare arm_aapcs_vfpcc float @sqrtf(float) readnone
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