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c793732c01
This new MIR pass removes redundant DBG_VALUEs. After the register allocator is done, more precisely, after the Virtual Register Rewriter, we end up having duplicated DBG_VALUEs, since some virtual registers are being rewritten into the same physical register as some of existing DBG_VALUEs. Each DBG_VALUE should indicate (at least before the LiveDebugValues) variables assignment, but it is being clobbered for function parameters during the SelectionDAG since it generates new DBG_VALUEs after COPY instructions, even though the parameter has no assignment. For example, if we had a DBG_VALUE $regX as an entry debug value representing the parameter, and a COPY and after the COPY, DBG_VALUE $virt_reg, and after the virtregrewrite the $virt_reg gets rewritten into $regX, we'd end up having redundant DBG_VALUE. This breaks the definition of the DBG_VALUE since some analysis passes might be built on top of that premise..., and this patch tries to fix the MIR with the respect to that. This first patch performs bacward scan, by trying to detect a sequence of consecutive DBG_VALUEs, and to remove all DBG_VALUEs describing one variable but the last one: For example: (1) DBG_VALUE $edi, !"var1", ... (2) DBG_VALUE $esi, !"var2", ... (3) DBG_VALUE $edi, !"var1", ... ... in this case, we can remove (1). By combining the forward scan that will be introduced in the next patch (from this stack), by inspecting the statistics, the RemoveRedundantDebugValues removes 15032 instructions by using gdb-7.11 as a testbed. Differential Revision: https://reviews.llvm.org/D105279
194 lines
9.2 KiB
LLVM
194 lines
9.2 KiB
LLVM
; RUN: llc -mtriple=arm -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | grep -v "Verify generated machine code" | FileCheck %s
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; REQUIRES: asserts
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; CHECK: ModulePass Manager
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; CHECK-NEXT: Pre-ISel Intrinsic Lowering
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; CHECK-NEXT: FunctionPass Manager
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; CHECK-NEXT: Expand Atomic instructions
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; CHECK-NEXT: Simplify the CFG
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; CHECK-NEXT: Dominator Tree Construction
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; CHECK-NEXT: Natural Loop Information
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; CHECK-NEXT: MVE gather/scatter lowering
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; CHECK-NEXT: MVE lane interleaving
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; CHECK-NEXT: Module Verifier
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; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
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; CHECK-NEXT: Canonicalize natural loops
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; CHECK-NEXT: Scalar Evolution Analysis
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; CHECK-NEXT: Loop Pass Manager
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; CHECK-NEXT: Canonicalize Freeze Instructions in Loops
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; CHECK-NEXT: Induction Variable Users
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; CHECK-NEXT: Loop Strength Reduction
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; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
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; CHECK-NEXT: Function Alias Analysis Results
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; CHECK-NEXT: Merge contiguous icmps into a memcmp
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; CHECK-NEXT: Natural Loop Information
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; CHECK-NEXT: Lazy Branch Probability Analysis
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; CHECK-NEXT: Lazy Block Frequency Analysis
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; CHECK-NEXT: Expand memcmp() to load/stores
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; CHECK-NEXT: Lower Garbage Collection Instructions
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; CHECK-NEXT: Shadow Stack GC Lowering
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; CHECK-NEXT: Lower constant intrinsics
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; CHECK-NEXT: Remove unreachable blocks from the CFG
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; CHECK-NEXT: Natural Loop Information
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; CHECK-NEXT: Post-Dominator Tree Construction
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; CHECK-NEXT: Branch Probability Analysis
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; CHECK-NEXT: Block Frequency Analysis
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; CHECK-NEXT: Constant Hoisting
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; CHECK-NEXT: Replace intrinsics with calls to vector library
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; CHECK-NEXT: Partially inline calls to library functions
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; CHECK-NEXT: Expand vector predication intrinsics
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; CHECK-NEXT: Scalarize Masked Memory Intrinsics
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; CHECK-NEXT: Expand reduction intrinsics
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; CHECK-NEXT: Natural Loop Information
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; CHECK-NEXT: Scalar Evolution Analysis
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; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
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; CHECK-NEXT: Function Alias Analysis Results
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; CHECK-NEXT: Transform functions to use DSP intrinsics
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; CHECK-NEXT: Interleaved Access Pass
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; CHECK-NEXT: Type Promotion
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; CHECK-NEXT: Dominator Tree Construction
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; CHECK-NEXT: Natural Loop Information
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; CHECK-NEXT: CodeGen Prepare
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; CHECK-NEXT: Dominator Tree Construction
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; CHECK-NEXT: Exception handling preparation
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; CHECK-NEXT: Merge internal globals
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; CHECK-NEXT: Natural Loop Information
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; CHECK-NEXT: Scalar Evolution Analysis
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; CHECK-NEXT: Lazy Branch Probability Analysis
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; CHECK-NEXT: Lazy Block Frequency Analysis
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; CHECK-NEXT: Optimization Remark Emitter
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; CHECK-NEXT: Hardware Loop Insertion
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; CHECK-NEXT: Scalar Evolution Analysis
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; CHECK-NEXT: Loop Pass Manager
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; CHECK-NEXT: Transform predicated vector loops to use MVE tail predication
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; CHECK-NEXT: A No-Op Barrier Pass
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; CHECK-NEXT: FunctionPass Manager
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; CHECK-NEXT: Safe Stack instrumentation pass
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; CHECK-NEXT: Insert stack protectors
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; CHECK-NEXT: Module Verifier
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; CHECK-NEXT: Dominator Tree Construction
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; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
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; CHECK-NEXT: Function Alias Analysis Results
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; CHECK-NEXT: Natural Loop Information
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; CHECK-NEXT: Post-Dominator Tree Construction
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; CHECK-NEXT: Branch Probability Analysis
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; CHECK-NEXT: Lazy Branch Probability Analysis
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; CHECK-NEXT: Lazy Block Frequency Analysis
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; CHECK-NEXT: ARM Instruction Selection
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; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Early Tail Duplication
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; CHECK-NEXT: Optimize machine instruction PHIs
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; CHECK-NEXT: Slot index numbering
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; CHECK-NEXT: Merge disjoint stack slots
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; CHECK-NEXT: Local Stack Slot Allocation
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; CHECK-NEXT: Remove dead machine instructions
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: Machine Block Frequency Analysis
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; CHECK-NEXT: Early Machine Loop Invariant Code Motion
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Block Frequency Analysis
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; CHECK-NEXT: Machine Common Subexpression Elimination
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; CHECK-NEXT: MachinePostDominator Tree Construction
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; CHECK-NEXT: Machine code sinking
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; CHECK-NEXT: Peephole Optimizations
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; CHECK-NEXT: Remove dead machine instructions
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: MVE TailPred and VPT Optimisation Pass
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; CHECK-NEXT: ARM MLA / MLS expansion pass
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: ARM pre- register allocation load / store optimization pass
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; CHECK-NEXT: ARM A15 S->D optimizer
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; CHECK-NEXT: Detect Dead Lanes
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; CHECK-NEXT: Process Implicit Definitions
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; CHECK-NEXT: Remove unreachable machine basic blocks
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; CHECK-NEXT: Live Variable Analysis
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: Eliminate PHI nodes for register allocation
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; CHECK-NEXT: Two-Address instruction pass
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; CHECK-NEXT: Slot index numbering
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; CHECK-NEXT: Live Interval Analysis
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; CHECK-NEXT: Simple Register Coalescing
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; CHECK-NEXT: Rename Disconnected Subregister Components
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; CHECK-NEXT: Machine Instruction Scheduler
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; CHECK-NEXT: Machine Block Frequency Analysis
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; CHECK-NEXT: Debug Variable Analysis
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; CHECK-NEXT: Live Stack Slot Analysis
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; CHECK-NEXT: Virtual Register Map
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; CHECK-NEXT: Live Register Matrix
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; CHECK-NEXT: Bundle Machine CFG Edges
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; CHECK-NEXT: Spill Code Placement Analysis
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Machine Optimization Remark Emitter
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; CHECK-NEXT: Greedy Register Allocator
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; CHECK-NEXT: Virtual Register Rewriter
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; CHECK-NEXT: Stack Slot Coloring
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; CHECK-NEXT: Machine Copy Propagation Pass
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; CHECK-NEXT: Machine Loop Invariant Code Motion
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; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis
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; CHECK-NEXT: Fixup Statepoint Caller Saved
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; CHECK-NEXT: PostRA Machine Sink
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; CHECK-NEXT: Machine Block Frequency Analysis
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: MachinePostDominator Tree Construction
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Machine Optimization Remark Emitter
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; CHECK-NEXT: Shrink Wrapping analysis
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; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization
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; CHECK-NEXT: Control Flow Optimizer
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Tail Duplication
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; CHECK-NEXT: Machine Copy Propagation Pass
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; CHECK-NEXT: Post-RA pseudo instruction expansion pass
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; CHECK-NEXT: ARM load / store optimization pass
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; CHECK-NEXT: ReachingDefAnalysis
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; CHECK-NEXT: ARM Execution Domain Fix
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; CHECK-NEXT: BreakFalseDeps
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; CHECK-NEXT: ARM pseudo instruction expansion pass
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; CHECK-NEXT: Thumb2 instruction size reduce pass
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: Machine Block Frequency Analysis
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; CHECK-NEXT: If Converter
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; CHECK-NEXT: MVE VPT block insertion pass
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; CHECK-NEXT: Thumb IT blocks insertion pass
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: PostRA Machine Instruction Scheduler
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; CHECK-NEXT: Post RA top-down list latency scheduler
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; CHECK-NEXT: ARM Indirect Thunks
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; CHECK-NEXT: ARM sls hardening pass
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; CHECK-NEXT: Analyze Machine Code For Garbage Collection
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: Machine Block Frequency Analysis
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; CHECK-NEXT: MachinePostDominator Tree Construction
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; CHECK-NEXT: Branch Probability Basic Block Placement
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; CHECK-NEXT: Insert fentry calls
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; CHECK-NEXT: Insert XRay ops
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; CHECK-NEXT: Implement the 'patchable-function' attribute
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; CHECK-NEXT: Thumb2 instruction size reduce pass
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; CHECK-NEXT: Unpack machine instruction bundles
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: ARM block placement
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; CHECK-NEXT: optimise barriers pass
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; CHECK-NEXT: Contiguously Lay Out Funclets
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; CHECK-NEXT: StackMap Liveness Analysis
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; CHECK-NEXT: Live DEBUG_VALUE analysis
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; CHECK-NEXT: Machine Outliner
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; CHECK-NEXT: FunctionPass Manager
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: ARM constant island placement and branch shortening pass
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: ReachingDefAnalysis
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; CHECK-NEXT: ARM Low Overhead Loops pass
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Machine Optimization Remark Emitter
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; CHECK-NEXT: ARM Assembly Printer
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; CHECK-NEXT: Free MachineFunction
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