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f5046224cf
Fold
VT = (and (sign_extend NarrowVT to VT) #bitmask)
into
VT = (zero_extend NarrowVT)
With this combine, the test replaces a sign extended load + an
unsigned extention with a zero extended load to render one of the
operands of the last multiplication.
BEFORE | AFTER
f_i16_i32: | f_i16_i32:
.fnstart | .fnstart
ldrsh r0, [r0] | ldrh r1, [r1]
ldrsh r1, [r1] | ldrsh r0, [r0]
smulbb r0, r1, r0 | smulbb r0, r0, r1
uxth r1, r1 | mul r0, r0, r1
mul r0, r0, r1 | bx lr
bx lr |
Reviewed By: resistor
Differential Revision: https://reviews.llvm.org/D90605
30 lines
1.0 KiB
LLVM
30 lines
1.0 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - -O3 \
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; RUN: -asm-verbose=0 | FileCheck %s
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; This tests exerts the folding of `VT = (and (sign_extend NarrowVT to
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; VT) #bitmask)` into `VT = (zero_extend NarrowVT to VT)` when
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; #bitmask value is the mask made by all ones that selects the value
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; of type NarrowVT inside the value of type VT. The folding is
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; implemented in `DAGCombiner::visitAND`.
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; With this the folding, the `and` of the "signed extended load" of
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; `%b` in `f_i16_i32` is rendered as a zero extended load.
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; CHECK-LABEL: f_i16_i32:
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; CHECK-NEXT: .fnstart
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; CHECK-NEXT: ldrh r1, [r1]
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; CHECK-NEXT: ldrsh r0, [r0]
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; CHECK-NEXT: smulbb r0, r0, r1
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; CHECK-NEXT: mul r0, r0, r1
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; CHECK-NEXT: bx lr
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define i32 @f_i16_i32(i16* %a, i16* %b) {
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%1 = load i16, i16* %a, align 2
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%sext.1 = sext i16 %1 to i32
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%2 = load i16, i16* %b, align 2
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%sext.2 = sext i16 %2 to i32
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%masked = and i32 %sext.2, 65535
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%mul = mul nsw i32 %sext.2, %sext.1
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%count.next = mul i32 %mul, %masked
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ret i32 %count.next
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}
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