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8ad0b9cbfb
The following: https://reviews.llvm.org/D82552 fixed an assert in the SelectionDag ISel legalizer for some CCs on armv7. I noticed that this fix also fixes the assert when using fastcc, so I am adding a fastcc regression test here. Differential Revision: https://reviews.llvm.org/D82443
82 lines
2.7 KiB
LLVM
82 lines
2.7 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7s-apple-ios7.0.0 | FileCheck %s
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define arm_aapcs_vfpcc { <8 x half>, <8 x half> } @f1() {
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; CHECK-LABEL: _f1
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; CHECK: vpush {d8}
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; CHECK-NEXT: vmov.f64 d8, #5.000000e-01
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; CHECK-NEXT: vmov.i32 d8, #0x0
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; CHECK-NEXT: vmov.i32 d0, #0x0
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; CHECK-NEXT: vmov.i32 d1, #0x0
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; CHECK-NEXT: vmov.i32 d2, #0x0
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; CHECK-NEXT: vmov.i32 d3, #0x0
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; CHECK-NEXT: vmov.i32 d4, #0x0
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; CHECK-NEXT: vmov.i32 d5, #0x0
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; CHECK-NEXT: vmov.i32 d6, #0x0
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; CHECK-NEXT: vmov.i32 d7, #0x0
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; CHECK-NEXT: vmov.f32 s1, s16
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; CHECK-NEXT: vmov.f32 s3, s16
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; CHECK-NEXT: vmov.f32 s5, s16
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; CHECK-NEXT: vmov.f32 s7, s16
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; CHECK-NEXT: vmov.f32 s9, s16
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; CHECK-NEXT: vmov.f32 s11, s16
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; CHECK-NEXT: vmov.f32 s13, s16
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; CHECK-NEXT: vmov.f32 s15, s16
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; CHECK-NEXT: vpop {d8}
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; CHECK-NEXT: bx lr
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ret { <8 x half>, <8 x half> } zeroinitializer
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}
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define swiftcc { <8 x half>, <8 x half> } @f2() {
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; CHECK-LABEL: _f2
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; CHECK: vpush {d8}
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; CHECK-NEXT: vmov.f64 d8, #5.000000e-01
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; CHECK-NEXT: vmov.i32 d8, #0x0
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; CHECK-NEXT: vmov.i32 d0, #0x0
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; CHECK-NEXT: vmov.i32 d1, #0x0
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; CHECK-NEXT: vmov.i32 d2, #0x0
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; CHECK-NEXT: vmov.i32 d3, #0x0
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; CHECK-NEXT: vmov.i32 d4, #0x0
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; CHECK-NEXT: vmov.i32 d5, #0x0
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; CHECK-NEXT: vmov.i32 d6, #0x0
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; CHECK-NEXT: vmov.i32 d7, #0x0
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; CHECK-NEXT: vmov.f32 s1, s16
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; CHECK-NEXT: vmov.f32 s3, s16
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; CHECK-NEXT: vmov.f32 s5, s16
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; CHECK-NEXT: vmov.f32 s7, s16
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; CHECK-NEXT: vmov.f32 s9, s16
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; CHECK-NEXT: vmov.f32 s11, s16
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; CHECK-NEXT: vmov.f32 s13, s16
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; CHECK-NEXT: vmov.f32 s15, s16
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; CHECK-NEXT: vpop {d8}
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; CHECK-NEXT: bx lr
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ret { <8 x half>, <8 x half> } zeroinitializer
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}
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define fastcc { <8 x half>, <8 x half> } @f3() {
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; CHECK-LABEL: _f3
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; CHECK: vpush {d8}
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; CHECK-NEXT: vmov.f64 d8, #5.000000e-01
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; CHECK-NEXT: vmov.i32 d8, #0x0
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; CHECK-NEXT: vmov.i32 d0, #0x0
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; CHECK-NEXT: vmov.i32 d1, #0x0
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; CHECK-NEXT: vmov.i32 d2, #0x0
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; CHECK-NEXT: vmov.i32 d3, #0x0
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; CHECK-NEXT: vmov.i32 d4, #0x0
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; CHECK-NEXT: vmov.i32 d5, #0x0
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; CHECK-NEXT: vmov.i32 d6, #0x0
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; CHECK-NEXT: vmov.i32 d7, #0x0
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; CHECK-NEXT: vmov.f32 s1, s16
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; CHECK-NEXT: vmov.f32 s3, s16
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; CHECK-NEXT: vmov.f32 s5, s16
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; CHECK-NEXT: vmov.f32 s7, s16
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; CHECK-NEXT: vmov.f32 s9, s16
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; CHECK-NEXT: vmov.f32 s11, s16
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; CHECK-NEXT: vmov.f32 s13, s16
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; CHECK-NEXT: vmov.f32 s15, s16
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; CHECK-NEXT: vpop {d8}
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; CHECK-NEXT: bx lr
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ret { <8 x half>, <8 x half> } zeroinitializer
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}
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