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c955b9f411
This patch adds codegen for the following BFloat operations to the ARM backend: * concatenation of bf16 vectors * bf16 vector element extraction * bf16 vector element insertion * duplication of a bf16 value into each lane of a vector * duplication of a bf16 vector lane into each lane Differential Revision: https://reviews.llvm.org/D81411
46 lines
1.4 KiB
LLVM
46 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=armv8.6a-arm-none-eabi -mattr=+bf16,+neon,+fullfp16 < %s | FileCheck %s
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "armv8.6a-arm-none-eabi"
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define arm_aapcs_vfpcc bfloat @test_vgetq_lane_bf16_even(<8 x bfloat> %v) {
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; CHECK-LABEL: test_vgetq_lane_bf16_even:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f32 s0, s3
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; CHECK-NEXT: bx lr
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entry:
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%0 = extractelement <8 x bfloat> %v, i32 6
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ret bfloat %0
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}
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define arm_aapcs_vfpcc bfloat @test_vgetq_lane_bf16_odd(<8 x bfloat> %v) {
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; CHECK-LABEL: test_vgetq_lane_bf16_odd:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovx.f16 s0, s3
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; CHECK-NEXT: bx lr
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entry:
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%0 = extractelement <8 x bfloat> %v, i32 7
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ret bfloat %0
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}
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define arm_aapcs_vfpcc bfloat @test_vget_lane_bf16_even(<4 x bfloat> %v) {
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; CHECK-LABEL: test_vget_lane_bf16_even:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov.f32 s0, s1
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; CHECK-NEXT: bx lr
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entry:
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%0 = extractelement <4 x bfloat> %v, i32 2
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ret bfloat %0
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}
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define arm_aapcs_vfpcc bfloat @test_vget_lane_bf16_odd(<4 x bfloat> %v) {
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; CHECK-LABEL: test_vget_lane_bf16_odd:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovx.f16 s0, s0
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; CHECK-NEXT: bx lr
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entry:
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%0 = extractelement <4 x bfloat> %v, i32 1
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ret bfloat %0
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}
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