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76b9d74d69
Summary: Fix read of uninitialized RC variable in ARM's PrintAsmOperand when hasRegClassConstraint returns false. This was causing inline-asm-operand-implicit-cast test to fail in r338206. Reviewers: t.p.northover, weimingz, javed.absar, chill Reviewed By: chill Subscribers: chill, eraman, kristof.beyls, chrib, llvm-commits Differential Revision: https://reviews.llvm.org/D49984 llvm-svn: 338268
115 lines
5.6 KiB
LLVM
115 lines
5.6 KiB
LLVM
; RUN: llc < %s -O3 -mtriple=arm-linux-gnueabi -no-integrated-as | FileCheck %s
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; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs -no-integrated-as < %s | FileCheck %s
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; check if regs are passing correctly
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define void @i64_write(i64* %p, i64 %val) nounwind {
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; CHECK-LABEL: i64_write:
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
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%1 = tail call i64 asm sideeffect "1: ldrexd $0, ${0:H}, [$2]\0A strexd $0, $3, ${3:H}, [$2]\0A teq $0, #0\0A bne 1b", "=&r,=*Qo,r,r,~{cc}"(i64* %p, i64* %p, i64 %val) nounwind
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ret void
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}
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; check if register allocation can reuse the registers
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define void @multi_writes(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind {
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entry:
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; CHECK-LABEL: multi_writes:
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
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%incdec.ptr = getelementptr inbounds i64, i64* %p, i32 1
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tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
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tail call void asm sideeffect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, ${4:H}, [$0]\0A strexd $5, ${5:H}, [$0]\0A strexd $6, ${6:H}, [$0]\0A", "r,r,r,r,r,r,r"(i64* %incdec.ptr, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind
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ret void
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}
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; check if callee-saved registers used by inline asm are saved/restored
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define void @foo(i64* %p, i64 %i) nounwind {
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; CHECK-LABEL:foo:
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; CHECK: {{push|push.w}} {{{r[4-9]|r10|r11}}
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; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
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; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
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; CHECK: {{pop|pop.w}} {{{r[4-9]|r10|r11}}
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%1 = tail call { i64, i64 } asm sideeffect "@ atomic64_set\0A1: ldrexd $0, ${0:H}, [$3]\0Aldrexd $1, ${1:H}, [$3]\0A strexd $0, $4, ${4:H}, [$3]\0A teq $0, #0\0A bne 1b", "=&r,=&r,=*Qo,r,r,~{cc}"(i64* %p, i64* %p, i64 %i) nounwind
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ret void
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}
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; return *p;
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define i64 @ldrd_test(i64* %p) nounwind {
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; CHECK-LABEL: ldrd_test:
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%1 = tail call i64 asm "ldrd $0, ${0:H}, [$1]", "=r,r"(i64* %p) nounwind
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ret i64 %1
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}
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define i64 @QR_test(i64* %p) nounwind {
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; CHECK-LABEL: QR_test:
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; CHECK: ldrd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
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%1 = tail call i64 asm "ldrd ${0:Q}, ${0:R}, [$1]", "=r,r"(i64* %p) nounwind
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ret i64 %1
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}
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define i64 @defuse_test(i64 %p) nounwind {
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; CHECK-LABEL: defuse_test:
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; CHECK: add {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, #1
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%1 = tail call i64 asm "add $0, ${0:H}, #1", "=r,0"(i64 %p) nounwind
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ret i64 %1
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}
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; *p = (hi << 32) | lo;
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define void @strd_test(i64* %p, i32 %lo, i32 %hi) nounwind {
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; CHECK-LABEL: strd_test:
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; CHECK: strd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
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%1 = zext i32 %hi to i64
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%2 = shl nuw i64 %1, 32
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%3 = sext i32 %lo to i64
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%4 = or i64 %2, %3
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tail call void asm sideeffect "strd $0, ${0:H}, [$1]", "r,r"(i64 %4, i64* %p) nounwind
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ret void
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}
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; Make sure we don't untie operands by mistake.
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define i64 @tied_64bit_test(i64 %in) nounwind {
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; CHECK-LABEL: tied_64bit_test:
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; CHECK: OUT([[OUTREG:r[0-9]+]]), IN([[OUTREG]])
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%addr = alloca i64
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call void asm "OUT($0), IN($1)", "=*rm,0"(i64* %addr, i64 %in)
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ret i64 %in
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}
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; If we explicitly name a tied operand, then the code should lookup the operand
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; we were tied to for information about register class and so on.
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define i64 @tied_64bit_lookback_test(i64 %in) nounwind {
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; CHECK-LABEL: tied_64bit_lookback_test:
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; CHECK: OUTLO([[LO:r[0-9]+]]) OUTHI([[HI:r[0-9]+]]) INLO([[LO]]) INHI([[HI]])
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%vars = call {i64, i32, i64} asm "OUTLO(${2:Q}) OUTHI(${2:R}) INLO(${3:Q}) INHI(${3:R})", "=r,=r,=r,2"(i64 %in)
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%res = extractvalue {i64, i32, i64} %vars, 2
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ret i64 %res
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}
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; Check access to low and high part with a specific register pair constraint
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define i64 @low_high_specific_reg_pair(i64 %in) nounwind {
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; CHECK-LABEL: low_high_specific_reg_pair
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; CHECK: mov r3, r2
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%res = call i64 asm "mov ${0:R}, ${1:Q}", "=&{r2},0"(i64 %in)
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ret i64 %res
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}
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