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a1d7f2fdc1
Those two subtarget features were awkward because their semantics are reversed: each one indicates the _lack_ of support for something in the architecture, rather than the presence. As a consequence, you don't get the behavior you want if you combine two sets of feature bits. Each SubtargetFeature for an FP architecture version now comes in four versions, one for each combination of those options. So you can still say (for example) '+vfp2' in a feature string and it will mean what it's always meant, but there's a new string '+vfp2d16sp' meaning the version without those extra options. A lot of this change is just mechanically replacing positive checks for the old features with negative checks for the new ones. But one more interesting change is that I've rearranged getFPUFeatures() so that the main FPU feature is appended to the output list *before* rather than after the features derived from the Restriction field, so that -fp64 and -d32 can override defaults added by the main feature. Reviewers: dmgreen, samparker, SjoerdMeijer Subscribers: srhines, javed.absar, eraman, kristof.beyls, hiraditya, zzheng, Petar.Avramovic, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D60691 llvm-svn: 361845
308 lines
12 KiB
LLVM
308 lines
12 KiB
LLVM
; RUN: llc -mtriple armv7-arm-linux-gnueabihf -O2 -mcpu=cortex-a7 < %s | FileCheck %s
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%struct.twofloat = type { float, float }
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%struct.twodouble = type { double, double }
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; Check support for returning a float in GPR with soft float ABI
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define arm_aapcscc float @zerobits_float_soft() #0 {
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; CHECK-LABEL: zerobits_float_soft
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; CHECK: mov r0, #0
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%1 = tail call float asm "mov ${0}, #0", "=&r"()
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ret float %1
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}
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; Check support for returning a double in GPR with soft float ABI
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define arm_aapcscc double @zerobits_double_soft() #0 {
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; CHECK-LABEL: zerobits_double_soft
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; CHECK: mov r0, #0
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; CHECK-NEXT: mov r1, #0
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%1 = tail call double asm "mov ${0:Q}, #0\0Amov ${0:R}, #0", "=&r"()
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ret double %1
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}
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; Check support for returning a float in GPR with matching float input with
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; soft float ABI
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define arm_aapcscc float @flt_gpr_matching_in_op_soft(float %f) #0 {
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; CHECK-LABEL: flt_gpr_matching_in_op_soft
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; CHECK: mov r0, r0
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%1 = call float asm "mov $0, $1", "=&r,0"(float %f)
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ret float %1
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}
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; Check support for returning a double in GPR with matching double input with
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; soft float ABI
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define arm_aapcscc double @dbl_gpr_matching_in_op_soft(double %d) #0 {
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; CHECK-LABEL: dbl_gpr_matching_in_op_soft
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; CHECK: mov r1, r0
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%1 = call double asm "mov ${0:R}, ${1:Q}", "=&r,0"(double %d)
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ret double %1
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}
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; Check support for returning a float in specific GPR with matching float input
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; with soft float ABI
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define arm_aapcscc float @flt_gpr_matching_spec_reg_in_op_soft(float %f) #0 {
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; CHECK-LABEL: flt_gpr_matching_spec_reg_in_op_soft
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; CHECK: mov r3, r3
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%1 = call float asm "mov $0, $1", "=&{r3},0"(float %f)
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ret float %1
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}
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; Check support for returning a double in specific GPR with matching double
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; input with soft float ABI
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define arm_aapcscc double @dbl_gpr_matching_spec_reg_in_op_soft(double %d) #0 {
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; CHECK-LABEL: dbl_gpr_matching_spec_reg_in_op_soft
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; CHECK: mov r3, r2
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%1 = call double asm "mov ${0:R}, ${1:Q}", "=&{r2},0"(double %d)
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ret double %1
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}
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; Check support for returning several float in GPR
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define arm_aapcscc float @zerobits_float_convoluted_soft() #0 {
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; CHECK-LABEL: zerobits_float_convoluted_soft
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; CHECK: mov r0, #0
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; CHECK-NEXT: mov r1, #0
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%1 = call { float, float } asm "mov $0, #0; mov $1, #0", "=r,=r"()
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%asmresult = extractvalue { float, float } %1, 0
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%asmresult1 = extractvalue { float, float } %1, 1
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%add = fadd float %asmresult, %asmresult1
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ret float %add
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}
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; Check support for returning several double in GPR
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define double @zerobits_double_convoluted_soft() #0 {
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; CHECK-LABEL: zerobits_double_convoluted_soft
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; CHECK: mov r0, #0
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; CHECK-NEXT: mov r1, #0
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; CHECK-NEXT: mov r2, #0
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; CHECK-NEXT: mov r3, #0
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%1 = call { double, double } asm "mov ${0:Q}, #0; mov ${0:R}, #0; mov ${1:Q}, #0; mov ${1:R}, #0", "=r,=r"()
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%asmresult = extractvalue { double, double } %1, 0
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%asmresult1 = extractvalue { double, double } %1, 1
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%add = fadd double %asmresult, %asmresult1
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ret double %add
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}
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; Check support for returning several floats in GPRs with matching float inputs
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; with soft float ABI
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define arm_aapcscc float @flt_gprs_matching_in_op_soft(float %f1, float %f2) #0 {
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; CHECK-LABEL: flt_gprs_matching_in_op_soft
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; CHECK: mov r0, r0
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; CHECK-NEXT: mov r1, r1
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%1 = call { float, float } asm "mov $0, $2; mov $1, $3", "=&r,=&r,0,1"(float %f1, float %f2)
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%asmresult1 = extractvalue { float, float } %1, 0
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%asmresult2 = extractvalue { float, float } %1, 1
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%add = fadd float %asmresult1, %asmresult2
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ret float %add
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}
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; Check support for returning several double in GPRs with matching double input
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; with soft float ABI
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define arm_aapcscc double @dbl_gprs_matching_in_op_soft(double %d1, double %d2) #0 {
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; CHECK-LABEL: dbl_gprs_matching_in_op_soft
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; CHECK: mov r1, r0
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; CHECK-NEXT: mov r3, r2
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%1 = call { double, double } asm "mov ${0:R}, ${2:Q}; mov ${1:R}, ${3:Q}", "=&r,=&r,0,1"(double %d1, double %d2)
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%asmresult1 = extractvalue { double, double } %1, 0
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%asmresult2 = extractvalue { double, double } %1, 1
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%add = fadd double %asmresult1, %asmresult2
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ret double %add
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}
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; Check support for returning several float in specific GPRs with matching
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; float input with soft float ABI
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define arm_aapcscc float @flt_gprs_matching_spec_reg_in_op_soft(float %f1, float %f2) #0 {
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; CHECK-LABEL: flt_gprs_matching_spec_reg_in_op_soft
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; CHECK: mov r3, r3
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; CHECK-NEXT: mov r4, r4
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%1 = call { float, float } asm "mov $0, $2; mov $1, $3", "=&{r3},=&{r4},0,1"(float %f1, float %f2)
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%asmresult1 = extractvalue { float, float } %1, 0
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%asmresult2 = extractvalue { float, float } %1, 1
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%add = fadd float %asmresult1, %asmresult2
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ret float %add
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}
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; Check support for returning several double in specific GPRs with matching
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; double input with soft float ABI
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define arm_aapcscc double @dbl_gprs_matching_spec_reg_in_op_soft(double %d1, double %d2) #0 {
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; CHECK-LABEL: dbl_gprs_matching_spec_reg_in_op_soft
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; CHECK: mov r3, r2
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; CHECK-NEXT: mov r5, r4
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%1 = call { double, double } asm "mov ${0:R}, ${2:Q}; mov ${1:R}, ${3:Q}", "=&{r2},=&{r4},0,1"(double %d1, double %d2)
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%asmresult1 = extractvalue { double, double } %1, 0
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%asmresult2 = extractvalue { double, double } %1, 1
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%add = fadd double %asmresult1, %asmresult2
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ret double %add
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}
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attributes #0 = { nounwind "target-features"="-d32,+vfp2,+vfp3" "use-soft-float"="true" }
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; Check support for returning a float in GPR with hard float ABI
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define float @zerobits_float_hard() #1 {
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; CHECK-LABEL: zerobits_float_hard
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; CHECK: mov r0, #0
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; CHECK: vmov s0, r0
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%1 = tail call float asm "mov ${0}, #0", "=&r"()
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ret float %1
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}
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; Check support for returning a double in GPR with hard float ABI
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define double @zerobits_double_hard() #1 {
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; CHECK-LABEL: zerobits_double_hard
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; CHECK: mov r0, #0
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; CHECK-NEXT: mov r1, #0
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; CHECK: vmov d0, r0, r1
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%1 = tail call double asm "mov ${0:Q}, #0\0Amov ${0:R}, #0", "=&r"()
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ret double %1
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}
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; Check support for returning a float in GPR with matching float input with
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; hard float ABI
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define float @flt_gpr_matching_in_op_hard(float %f) #1 {
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; CHECK-LABEL: flt_gpr_matching_in_op_hard
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; CHECK: vmov r0, s0
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; CHECK: mov r0, r0
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; CHECK: vmov s0, r0
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%1 = call float asm "mov $0, $1", "=&r,0"(float %f)
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ret float %1
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}
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; Check support for returning a double in GPR with matching double input with
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; hard float ABI
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define double @dbl_gpr_matching_in_op_hard(double %d) #1 {
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; CHECK-LABEL: dbl_gpr_matching_in_op_hard
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; CHECK: vmov r0, r1, d0
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; CHECK: mov r1, r0
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; CHECK: vmov d0, r0, r1
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%1 = call double asm "mov ${0:R}, ${1:Q}", "=&r,0"(double %d)
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ret double %1
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}
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; Check support for returning a float in specific GPR with matching float
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; input with hard float ABI
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define float @flt_gpr_matching_spec_reg_in_op_hard(float %f) #1 {
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; CHECK-LABEL: flt_gpr_matching_spec_reg_in_op_hard
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; CHECK: vmov r3, s0
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; CHECK: mov r3, r3
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; CHECK: vmov s0, r3
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%1 = call float asm "mov $0, $1", "=&{r3},0"(float %f)
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ret float %1
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}
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; Check support for returning a double in specific GPR with matching double
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; input with hard float ABI
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define double @dbl_gpr_matching_spec_reg_in_op_hard(double %d) #1 {
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; CHECK-LABEL: dbl_gpr_matching_spec_reg_in_op_hard
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; CHECK: vmov r2, r3, d0
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; CHECK: mov r3, r2
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; CHECK: vmov d0, r2, r3
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%1 = call double asm "mov ${0:R}, ${1:Q}", "=&{r2},0"(double %d)
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ret double %1
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}
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; Check support for returning several float in GPR
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define %struct.twofloat @zerobits_float_convoluted_hard() #1 {
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; CHECK-LABEL: zerobits_float_convoluted_hard
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; CHECK: mov r0, #0
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; CHECK-NEXT: mov r1, #0
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; CHECK: vmov s0, r0
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; CHECK-NEXT: vmov s1, r1
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%1 = call { float, float } asm "mov $0, #0; mov $1, #0", "=r,=r"()
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%asmresult1 = extractvalue { float, float } %1, 0
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%asmresult2 = extractvalue { float, float } %1, 1
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%partialres = insertvalue %struct.twofloat undef, float %asmresult1, 0
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%res = insertvalue %struct.twofloat %partialres, float %asmresult2, 1
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ret %struct.twofloat %res
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}
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; Check support for returning several double in GPR
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define %struct.twodouble @zerobits_double_convoluted_hard() #1 {
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; CHECK-LABEL: zerobits_double_convoluted_hard
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; CHECK: mov r0, #0
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; CHECK-NEXT: mov r1, #0
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; CHECK-NEXT: mov r2, #0
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; CHECK-NEXT: mov r3, #0
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; CHECK: vmov d0, r0, r1
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; CHECK-NEXT: vmov d1, r2, r3
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%1 = call { double, double } asm "mov ${0:Q}, #0; mov ${0:R}, #0; mov ${1:Q}, #0; mov ${1:R}, #0", "=r,=r"()
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%asmresult1 = extractvalue { double, double } %1, 0
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%asmresult2 = extractvalue { double, double } %1, 1
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%partialres = insertvalue %struct.twodouble undef, double %asmresult1, 0
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%res = insertvalue %struct.twodouble %partialres, double %asmresult2, 1
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ret %struct.twodouble %res
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}
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; Check support for returning several floats in GPRs with matching float inputs
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; with hard float ABI
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define %struct.twofloat @flt_gprs_matching_in_op_hard(float %f1, float %f2) #1 {
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; CHECK-LABEL: flt_gprs_matching_in_op_hard
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; CHECK: vmov r0, s0
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; CHECK-NEXT: vmov r1, s1
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; CHECK: mov r0, r0
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; CHECK-NEXT: mov r1, r1
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; CHECK: vmov s0, r0
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; CHECK-NEXT: vmov s1, r1
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%1 = call { float, float } asm "mov $0, $2; mov $1, $3", "=&r,=&r,0,1"(float %f1, float %f2)
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%asmresult1 = extractvalue { float, float } %1, 0
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%asmresult2 = extractvalue { float, float } %1, 1
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%partialres = insertvalue %struct.twofloat undef, float %asmresult1, 0
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%res = insertvalue %struct.twofloat %partialres, float %asmresult2, 1
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ret %struct.twofloat %res
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}
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; Check support for returning several double in GPRs with matching double input
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; with hard float ABI
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define %struct.twodouble @dbl_gprs_matching_in_op_hard(double %d1, double %d2) #1 {
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; CHECK-LABEL: dbl_gprs_matching_in_op_hard
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; CHECK: vmov r0, r1, d0
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; CHECK-NEXT: vmov r2, r3, d1
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; CHECK: mov r1, r0
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; CHECK-NEXT: mov r3, r2
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; CHECK: vmov d0, r0, r1
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; CHECK-NEXT: vmov d1, r2, r3
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%1 = call { double, double } asm "mov ${0:R}, ${2:Q}; mov ${1:R}, ${3:Q}", "=&r,=&r,0,1"(double %d1, double %d2)
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%asmresult1 = extractvalue { double, double } %1, 0
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%asmresult2 = extractvalue { double, double } %1, 1
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%partialres = insertvalue %struct.twodouble undef, double %asmresult1, 0
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%res = insertvalue %struct.twodouble %partialres, double %asmresult2, 1
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ret %struct.twodouble %res
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}
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; Check support for returning several float in specific GPRs with matching
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; float input with hard float ABI
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define %struct.twofloat @flt_gprs_matching_spec_reg_in_op_hard(float %f1, float %f2) #1 {
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; CHECK-LABEL: flt_gprs_matching_spec_reg_in_op_hard
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; CHECK: vmov r3, s0
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; CHECK-NEXT: vmov r4, s1
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; CHECK: mov r3, r3
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; CHECK-NEXT: mov r4, r4
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; CHECK: vmov s0, r3
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; CHECK-NEXT: vmov s1, r4
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%1 = call { float, float } asm "mov $0, $2; mov $1, $3", "=&{r3},=&{r4},0,1"(float %f1, float %f2)
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%asmresult1 = extractvalue { float, float } %1, 0
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%asmresult2 = extractvalue { float, float } %1, 1
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%partialres = insertvalue %struct.twofloat undef, float %asmresult1, 0
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%res = insertvalue %struct.twofloat %partialres, float %asmresult2, 1
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ret %struct.twofloat %res
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}
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; Check support for returning several double in specific GPRs with matching
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; double input with hard float ABI
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define %struct.twodouble @dbl_gprs_matching_spec_reg_in_op_hard(double %d1, double %d2) #1 {
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; CHECK-LABEL: dbl_gprs_matching_spec_reg_in_op_hard
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; CHECK: vmov r2, r3, d0
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; CHECK-NEXT: vmov r4, r5, d1
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; CHECK: mov r3, r2
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; CHECK-NEXT: mov r5, r4
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; CHECK: vmov d0, r2, r3
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; CHECK-NEXT: vmov d1, r4, r5
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%1 = call { double, double } asm "mov ${0:R}, ${2:Q}; mov ${1:R}, ${3:Q}", "=&{r2},=&{r4},0,1"(double %d1, double %d2)
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%asmresult1 = extractvalue { double, double } %1, 0
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%asmresult2 = extractvalue { double, double } %1, 1
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%partialres = insertvalue %struct.twodouble undef, double %asmresult1, 0
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%res = insertvalue %struct.twodouble %partialres, double %asmresult2, 1
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ret %struct.twodouble %res
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}
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attributes #1 = { nounwind "target-features"="-d32,+vfp2,+vfp3" "use-soft-float"="false" }
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