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llvm-mirror/test/CodeGen/ARM/memset-inline.ll
Nirav Dave 6655b5e078 [DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
Summary:
A number of optimizations are inhibited by single-use TokenFactors not
being merged into the TokenFactor using it. This makes we consider if
we can do the merge immediately.

Most tests changes here are due to the change in visitation causing
minor reorderings and associated reassociation of paired memory
operations.

CodeGen tests with non-reordering changes:

  X86/aligned-variadic.ll -- memory-based add folded into stored leaq
  value.

  X86/constant-combiners.ll -- Optimizes out overlap between stores.

  X86/pr40631_deadstore_elision -- folds constant byte store into
  preceding quad word constant store.

Reviewers: RKSimon, craig.topper, spatel, efriedma, courbet

Reviewed By: courbet

Subscribers: dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, eraman, hiraditya, kbarton, jrtc27, atanasyan, jsji, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59260

llvm-svn: 356068
2019-03-13 17:07:09 +00:00

94 lines
2.7 KiB
LLVM

; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -pre-RA-sched=source -disable-post-ra | FileCheck %s -check-prefix=CHECK-7A
; RUN: llc < %s -mtriple=thumbv6m -pre-RA-sched=source -disable-post-ra -mattr=+strict-align | FileCheck %s -check-prefix=CHECK-6M
define void @t1(i8* nocapture %c) nounwind optsize {
entry:
; CHECK-7A-LABEL: t1:
; CHECK-7A: movs r1, #0
; CHECK-7A: strd r1, r1, [r0]
; CHECK-7A: str r1, [r0, #8]
; CHECK-6M-LABEL: t1:
; CHECK-6M: movs r1, #0
; CHECK-6M: str r1, [r0]
; CHECK-6M: str r1, [r0, #4]
; CHECK-6M: str r1, [r0, #8]
call void @llvm.memset.p0i8.i64(i8* align 8 %c, i8 0, i64 12, i1 false)
ret void
}
define void @t2() nounwind ssp {
entry:
; CHECK-7A-LABEL: t2:
; CHECK-7A: vmov.i32 {{q[0-9]+}}, #0x0
; CHECK-7A: movs r1, #10
; CHECK-7A: vst1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r2], r1
; CHECK-7A: vst1.16 {d{{[0-9]+}}, d{{[0-9]+}}}, [r2]
; CHECK-6M-LABEL: t2:
; CHECK-6M: movs [[REG:r[0-9]+]], #0
; CHECK-6M-DAG: str [[REG]], [sp, #20]
; CHECK-6M-DAG: str [[REG]], [sp, #16]
; CHECK-6M-DAG: str [[REG]], [sp, #12]
; CHECK-6M-DAG: str [[REG]], [sp, #8]
; CHECK-6M-DAG: str [[REG]], [sp, #4]
; CHECK-6M-DAG: str [[REG]], [sp]
%buf = alloca [26 x i8], align 1
%0 = getelementptr inbounds [26 x i8], [26 x i8]* %buf, i32 0, i32 0
call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 26, i1 false)
call void @something(i8* %0) nounwind
ret void
}
define void @t3(i8* %p) {
entry:
; CHECK-7A-LABEL: t3:
; CHECK-7A: muls [[REG:r[0-9]+]],
; CHECK-7A: str [[REG]],
; CHECK-6M-LABEL: t3:
; CHECK-6M-NOT: muls
; CHECK-6M: strb [[REG:r[0-9]+]],
; CHECK-6M: strb [[REG]],
; CHECK-6M: strb [[REG]],
; CHECK-6M: strb [[REG]],
br label %for.body
for.body:
%i = phi i32 [ 0, %entry ], [ %inc, %for.body ]
%0 = trunc i32 %i to i8
call void @llvm.memset.p0i8.i32(i8* %p, i8 %0, i32 4, i1 false)
call void @something(i8* %p)
%inc = add nuw nsw i32 %i, 1
%exitcond = icmp eq i32 %inc, 255
br i1 %exitcond, label %for.end, label %for.body
for.end:
ret void
}
define void @t4(i8* %p) {
entry:
; CHECK-7A-LABEL: t4:
; CHECK-7A: muls [[REG:r[0-9]+]],
; CHECK-7A: str [[REG]],
; CHECK-6M-LABEL: t4:
; CHECK-6M: muls [[REG:r[0-9]+]],
; CHECK-6M: strh [[REG]],
; CHECK-6M: strh [[REG]],
br label %for.body
for.body:
%i = phi i32 [ 0, %entry ], [ %inc, %for.body ]
%0 = trunc i32 %i to i8
call void @llvm.memset.p0i8.i32(i8* align 2 %p, i8 %0, i32 4, i1 false)
call void @something(i8* %p)
%inc = add nuw nsw i32 %i, 1
%exitcond = icmp eq i32 %inc, 255
br i1 %exitcond, label %for.end, label %for.body
for.end:
ret void
}
declare void @something(i8*) nounwind
declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1) nounwind
declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind