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369756d5e4
Summary:
Additional filtering of undesired shifts for targets that do not support them efficiently.
Related with D69116 and D69120
Applies the TLI.getShiftAmountThreshold hook to prevent undesired generation of shifts for the following IR code:
```
define i16 @testShiftBits(i16 %a) {
entry:
%and = and i16 %a, -64
%cmp = icmp eq i16 %and, 64
%conv = zext i1 %cmp to i16
ret i16 %conv
}
define i16 @testShiftBits_11(i16 %a) {
entry:
%cmp = icmp ugt i16 %a, 63
%conv = zext i1 %cmp to i16
ret i16 %conv
}
define i16 @testShiftBits_12(i16 %a) {
entry:
%cmp = icmp ult i16 %a, 64
%conv = zext i1 %cmp to i16
ret i16 %conv
}
```
The attached diff file shows the piece code in TargetLowering that is responsible for the generation of shifts in relation to the IR above.
Before applying this patch, shifts will be generated to replace non-legal icmp immediates. However, shifts may be undesired if they are even more expensive for the target.
For all my previous patches in this series (cited above) I added test cases for the MSP430 target. However, in this case, the target is not suitable for showing improvements related with this patch, because the MSP430 does not implement "isLegalICmpImmediate". The default implementation returns always true, therefore the patched code in TargetLowering is never reached for that target. Targets implementing both "isLegalICmpImmediate" and "getShiftAmountThreshold" will benefit from this.
The differential effect of this patch can only be shown for the MSP430 by temporarily implementing "isLegalICmpImmediate" to return false for large immediates. This is simulated with the implementation of a command line flag that was incorporated in D69975
This patch belongs to a initiative to "relax" the generation of shifts by LLVM for targets requiring it
Reviewers: spatel, lebedev.ri, asl
Reviewed By: spatel
Subscribers: lenary, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D69326
51 lines
1.5 KiB
LLVM
51 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=msp430-- -msp430-no-legal-immediate=true < %s | FileCheck %s
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; Test case for the following transformation in TargetLowering::SimplifySetCC
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; (X & -256) == 256 -> (X >> 8) == 1
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define i16 @testSimplifySetCC_2(i16 %x) {
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; CHECK-LABEL: testSimplifySetCC_2:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: and #-64, r12
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; CHECK-NEXT: cmp #64, r12
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; CHECK-NEXT: mov r2, r12
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; CHECK-NEXT: rra r12
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; CHECK-NEXT: and #1, r12
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; CHECK-NEXT: ret
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entry:
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%and = and i16 %x, -64
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%cmp = icmp eq i16 %and, 64
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%conv = zext i1 %cmp to i16
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ret i16 %conv
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}
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; Test case for the following transformation in TargetLowering::SimplifySetCC
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; X > 0x0ffffffff -> (X >> 32) >= 1
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define i16 @testSimplifySetCC_3(i16 %x) {
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; CHECK-LABEL: testSimplifySetCC_3:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: cmp #64, r12
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; CHECK-NEXT: mov r2, r12
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; CHECK-NEXT: and #1, r12
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp ugt i16 %x, 63
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%conv = zext i1 %cmp to i16
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ret i16 %conv
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}
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; Test case for the following transformation in TargetLowering::SimplifySetCC
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; X < 0x100000000 -> (X >> 32) < 1
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define i16 @testSimplifySetCC_4(i16 %x) {
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; CHECK-LABEL: testSimplifySetCC_4:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: cmp #64, r12
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; CHECK-NEXT: mov #1, r12
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; CHECK-NEXT: bic r2, r12
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp ult i16 %x, 64
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%conv = zext i1 %cmp to i16
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ret i16 %conv
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}
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