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https://github.com/RPCS3/llvm-mirror.git
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a1334aac0e
Summary: Replaces ``` unsigned getShiftAmountThreshold(EVT VT) ``` by ``` bool shouldAvoidTransformToShift(EVT VT, unsigned amount) ``` thus giving more flexibility for targets to decide whether particular shift amounts must be considered expensive or not. Updates the MSP430 target with a custom implementation. This continues D69116, D69120, D69326 and updates them, so all of them must be committed before this. Existing tests apply, a few more have been added. Reviewers: asl, spatel Reviewed By: spatel Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70042
211 lines
6.0 KiB
LLVM
211 lines
6.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=msp430-- < %s | FileCheck %s
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; Check the following conversion in TargetLowering::SimplifySetCC
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; (X & 8) != 0 --> (X & 8) >> 3
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define i16 @testSimplifySetCC_0(i16 %x) {
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; CHECK-LABEL: testSimplifySetCC_0:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: bit #32, r12
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; CHECK-NEXT: mov r2, r12
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; CHECK-NEXT: and #1, r12
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; CHECK-NEXT: ret
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entry:
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%and = and i16 %x, 32
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%cmp = icmp ne i16 %and, 0
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%conv = zext i1 %cmp to i16
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ret i16 %conv
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}
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; Check the following conversion in TargetLowering::SimplifySetCC
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; (X & 8) == 8 --> (X & 8) >> 3
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define i16 @testSimplifySetCC_1(i16 %x) {
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; CHECK-LABEL: testSimplifySetCC_1:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: bit #32, r12
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; CHECK-NEXT: mov r2, r12
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; CHECK-NEXT: and #1, r12
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; CHECK-NEXT: ret
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entry:
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%and = and i16 %x, 32
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%cmp = icmp eq i16 %and, 32
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%conv = zext i1 %cmp to i16
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ret i16 %conv
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}
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; Check the following conversion in DAGCombiner::SimplifySelectCC
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; (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
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define i16 @testSimplifySelectCC_0(i16 %x, i16 %a) {
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; CHECK-LABEL: testSimplifySelectCC_0:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: mov r12, r14
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; CHECK-NEXT: clr r12
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; CHECK-NEXT: bit #2048, r14
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; CHECK-NEXT: jeq .LBB2_2
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; CHECK-NEXT: ; %bb.1: ; %entry
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; CHECK-NEXT: mov r13, r12
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; CHECK-NEXT: .LBB2_2: ; %entry
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; CHECK-NEXT: ret
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entry:
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%and = and i16 %x, 2048
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%cmp = icmp eq i16 %and, 0
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%cond = select i1 %cmp, i16 0, i16 %a
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ret i16 %cond
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}
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; Check the following conversion in DAGCombiner foldExtendedSignBitTest
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; sext i1 (setgt iN X, -1) --> sra (not X), (N - 1)
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define i16 @testExtendSignBit_0(i16 %x) {
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; CHECK-LABEL: testExtendSignBit_0:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: mov r12, r13
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; CHECK-NEXT: mov #-1, r12
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; CHECK-NEXT: tst r13
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; CHECK-NEXT: jge .LBB3_2
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; CHECK-NEXT: ; %bb.1: ; %entry
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; CHECK-NEXT: clr r12
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; CHECK-NEXT: .LBB3_2: ; %entry
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp sgt i16 %x, -1
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%cond = sext i1 %cmp to i16
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ret i16 %cond
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}
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; Check the following conversion in DAGCombiner foldExtendedSignBitTest
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; zext i1 (setgt iN X, -1) --> srl (not X), (N - 1)
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define i16 @testExtendSignBit_1(i16 %x) {
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; CHECK-LABEL: testExtendSignBit_1:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: mov r12, r13
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; CHECK-NEXT: mov #1, r12
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; CHECK-NEXT: tst r13
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; CHECK-NEXT: jge .LBB4_2
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; CHECK-NEXT: ; %bb.1: ; %entry
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; CHECK-NEXT: clr r12
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; CHECK-NEXT: .LBB4_2: ; %entry
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp sgt i16 %x, -1
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%cond = zext i1 %cmp to i16
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ret i16 %cond
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}
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; Check the following conversion in DAGCombiner::foldSelectCCToShiftAnd
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; select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
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define i16 @testShiftAnd_0(i16 %x, i16 %a) {
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; CHECK-LABEL: testShiftAnd_0:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: tst r12
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; CHECK-NEXT: jl .LBB5_2
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; CHECK-NEXT: ; %bb.1: ; %entry
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; CHECK-NEXT: clr r13
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; CHECK-NEXT: .LBB5_2: ; %entry
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; CHECK-NEXT: mov r13, r12
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp slt i16 %x, 0
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%cond = select i1 %cmp, i16 %a, i16 0
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ret i16 %cond
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}
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; Check the following conversion in DAGCombiner::foldSelectCCToShiftAnd
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; select_cc setlt X, 0, A, 0 -> "and (srl X, C2), A" iff A is a single-bit
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define i16 @testShiftAnd_1(i16 %x) {
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; CHECK-LABEL: testShiftAnd_1:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: mov r12, r13
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; CHECK-NEXT: mov #1, r12
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; CHECK-NEXT: tst r13
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; CHECK-NEXT: jl .LBB6_2
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; CHECK-NEXT: ; %bb.1: ; %entry
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; CHECK-NEXT: clr r12
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; CHECK-NEXT: .LBB6_2: ; %entry
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; CHECK-NEXT: add r12, r12
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp slt i16 %x, 0
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%cond = select i1 %cmp, i16 2, i16 0
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ret i16 %cond
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}
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; Check the following conversion in DAGCombiner::SimplifySelectCC
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; select C, 16, 0 -> shl C, 4
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define i16 @testSimplifySelectCC_1(i16 %a, i16 %b) {
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; CHECK-LABEL: testSimplifySelectCC_1:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: mov r12, r14
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; CHECK-NEXT: mov #32, r12
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; CHECK-NEXT: cmp r14, r13
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; CHECK-NEXT: jl .LBB7_2
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; CHECK-NEXT: ; %bb.1: ; %entry
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; CHECK-NEXT: clr r12
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; CHECK-NEXT: .LBB7_2: ; %entry
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp sgt i16 %a, %b
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%cond = select i1 %cmp, i16 32, i16 0
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ret i16 %cond
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}
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; Check the following conversion in TargetLowering::SimplifySetCC
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; (X & 8) != 0 --> (X & 8) >> 3
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define i16 @testSimplifySetCC_0_sh8(i16 %x) {
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; CHECK-LABEL: testSimplifySetCC_0_sh8:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: and #256, r12
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; CHECK-NEXT: swpb r12
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; CHECK-NEXT: ret
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entry:
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%and = and i16 %x, 256
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%cmp = icmp ne i16 %and, 0
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%conv = zext i1 %cmp to i16
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ret i16 %conv
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}
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; Check the following conversion in TargetLowering::SimplifySetCC
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; (X & 8) == 8 --> (X & 8) >> 3
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define i16 @testSimplifySetCC_1_sh8(i16 %x) {
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; CHECK-LABEL: testSimplifySetCC_1_sh8:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: and #256, r12
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; CHECK-NEXT: swpb r12
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; CHECK-NEXT: ret
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entry:
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%and = and i16 %x, 256
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%cmp = icmp eq i16 %and, 256
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%conv = zext i1 %cmp to i16
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ret i16 %conv
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}
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; Check the following conversion in DAGCombiner::foldSelectCCToShiftAnd
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; select_cc setlt X, 0, A, 0 -> "and (srl X, C2), A" iff A is a single-bit
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define i16 @testShiftAnd_1_sh8(i16 %x) {
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; CHECK-LABEL: testShiftAnd_1_sh8:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: swpb r12
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; CHECK-NEXT: and #128, r12
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp slt i16 %x, 0
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%cond = select i1 %cmp, i16 128, i16 0
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ret i16 %cond
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}
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; Check the following conversion in DAGCombiner::foldSelectCCToShiftAnd
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; select_cc setlt X, 0, A, 0 -> "and (srl X, C2), A" iff A is a single-bit
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define i16 @testShiftAnd_1_sh9(i16 %x) {
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; CHECK-LABEL: testShiftAnd_1_sh9:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: swpb r12
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; CHECK-NEXT: mov.b r12, r12
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; CHECK-NEXT: clrc
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; CHECK-NEXT: rrc r12
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; CHECK-NEXT: and #64, r12
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; CHECK-NEXT: ret
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entry:
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%cmp = icmp slt i16 %x, 0
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%cond = select i1 %cmp, i16 64, i16 0
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ret i16 %cond
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}
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