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f52566451e
Enable passing more vector arguments then available vector argument passing registers. Differential Revision: https://reviews.llvm.org/D96415
19 lines
829 B
LLVM
19 lines
829 B
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \
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; RUN: -vec-extabi -mtriple powerpc-ibm-aix-xcoff < %s | \
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; RUN: FileCheck %s --check-prefix=32BIT
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec \
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; RUN: -vec-extabi -mtriple powerpc64-ibm-aix-xcoff < %s | \
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; RUN: FileCheck %s --check-prefix=64BIT
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define dso_local <4 x i32> @vec_callee_stack(<4 x i32> %vr2, <4 x i32> %vr3, <4 x i32> %vr4, <4 x i32> %vr5, <4 x i32> %vr6, <4 x i32> %vr7, <4 x i32> %vr8, <4 x i32> %vr9, <4 x i32> %vr10, <4 x i32> %vr11, <4 x i32> %vr12, <4 x i32> %vr13, <4 x i32> %vSpill1, <4 x i32> %vSpill2) {
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entry:
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ret <4 x i32> %vSpill2
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}
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; 32BIT: addi [[SCRATCH:[0-9]+]], 1, 48
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; 32BIT-NEXT: lxvw4x 34, 0, [[SCRATCH]]
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; 64BIT: addi [[SCRATCH:[0-9]+]], 1, 64
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; 64BIT-NEXT: lxvw4x 34, 0, [[SCRATCH]]
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