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9f4ca39c11
This patch includes the following updates to the load/store refactoring effort introduced in D93370: - Update various VSX patterns that use to "force" an XForm, to instead just XForm. This allows the ability for the patterns to compute the most optimal addressing mode (and to produce a DForm instruction when possible) - Update pattern and test case for the LXVD2X/STXVD2X intrinsics - Update LIT test cases that use to use the XForm instruction to use the DForm instruction Differential Revision: https://reviews.llvm.org/D95115
55 lines
2.3 KiB
LLVM
55 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \
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; RUN: -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names < %s | \
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; RUN: FileCheck %s
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; Function Attrs: nounwind readnone speculatable
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declare <4 x float> @llvm.fmuladd.v4f32(<4 x float>, <4 x float>, <4 x float>) #0
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; Function Attrs: nounwind readnone speculatable
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declare { i32, i1 } @llvm.usub.with.overflow.i32(i32, i32) #0
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define void @draw_llvm_vs_variant0(<4 x float> %x) {
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; CHECK-LABEL: draw_llvm_vs_variant0:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxsd v3, 0(r3)
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; CHECK-NEXT: vmrghh v3, v3, v3
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; CHECK-NEXT: vextsh2w v3, v3
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; CHECK-NEXT: xvcvsxwsp vs0, v3
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; CHECK-NEXT: xxspltw vs0, vs0, 2
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; CHECK-NEXT: xvmaddasp vs0, v2, v2
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; CHECK-NEXT: stxv vs0, 0(r3)
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; CHECK-NEXT: blr
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entry:
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%.size = load i32, i32* undef
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%0 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %.size, i32 7)
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%1 = extractvalue { i32, i1 } %0, 0
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%2 = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %1, i32 0)
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%3 = extractvalue { i32, i1 } %2, 0
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%4 = select i1 false, i32 0, i32 %3
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%5 = xor i1 false, true
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%6 = sext i1 %5 to i32
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%7 = load <4 x i16>, <4 x i16>* undef, align 2
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%8 = extractelement <4 x i16> %7, i32 0
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%9 = sext i16 %8 to i32
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%10 = insertelement <4 x i32> undef, i32 %9, i32 0
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%11 = extractelement <4 x i16> %7, i32 1
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%12 = sext i16 %11 to i32
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%13 = insertelement <4 x i32> %10, i32 %12, i32 1
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%14 = extractelement <4 x i16> %7, i32 2
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%15 = sext i16 %14 to i32
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%16 = insertelement <4 x i32> %13, i32 %15, i32 2
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%17 = extractelement <4 x i16> %7, i32 3
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%18 = sext i16 %17 to i32
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%19 = insertelement <4 x i32> %16, i32 %18, i32 3
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%20 = sitofp <4 x i32> %19 to <4 x float>
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%21 = insertelement <4 x i32> undef, i32 %6, i32 0
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%22 = shufflevector <4 x i32> %21, <4 x i32> undef, <4 x i32> zeroinitializer
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%23 = bitcast <4 x float> %20 to <4 x i32>
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%24 = and <4 x i32> %23, %22
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%25 = bitcast <4 x i32> %24 to <4 x float>
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%26 = shufflevector <4 x float> %25, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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%27 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %x, <4 x float> %x, <4 x float> %26)
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store <4 x float> %27, <4 x float>* undef
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ret void
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}
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