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b4c3d240d2
Relaxing superclass constraint for VSX register classes helps reducing 32-byte spills and copies when register pressure is high. In test case affected, some of them introduces more copies due to new allocation order. However, this patch should not be the root cause, and we may be able to fix it in other places of register allocation. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D104006
228 lines
6.0 KiB
LLVM
228 lines
6.0 KiB
LLVM
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-BE
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define double @test1(<2 x i64> %a) {
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entry:
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; CHECK-LABEL: test1
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; CHECK: xxswapd [[SW:[0-9]+]], 34
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; CHECK: xscvsxddp 1, [[SW]]
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; CHECK-BE-LABEL: test1
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; CHECK-BE: xscvsxddp 1, 34
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%0 = extractelement <2 x i64> %a, i32 0
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%1 = sitofp i64 %0 to double
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ret double %1
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}
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define double @test2(<2 x i64> %a) {
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entry:
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; CHECK-LABEL: test2
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; CHECK: xscvsxddp 1, 34
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; CHECK-BE-LABEL: test2
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; CHECK-BE: xxswapd [[SW:[0-9]+]], 34
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; CHECK-BE: xscvsxddp 1, [[SW]]
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%0 = extractelement <2 x i64> %a, i32 1
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%1 = sitofp i64 %0 to double
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ret double %1
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}
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define float @test1f(<2 x i64> %a) {
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entry:
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; CHECK-LABEL: test1f
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; CHECK: xxswapd [[SW:[0-9]+]], 34
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; CHECK: xscvsxdsp 1, [[SW]]
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; CHECK-BE-LABEL: test1f
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; CHECK-BE: xscvsxdsp 1, 34
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%0 = extractelement <2 x i64> %a, i32 0
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%1 = sitofp i64 %0 to float
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ret float %1
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}
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define float @test2f(<2 x i64> %a) {
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entry:
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; CHECK-LABEL: test2f
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; CHECK: xscvsxdsp 1, 34
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; CHECK-BE-LABEL: test2f
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; CHECK-BE: xxswapd [[SW:[0-9]+]], 34
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; CHECK-BE: xscvsxdsp 1, [[SW]]
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%0 = extractelement <2 x i64> %a, i32 1
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%1 = sitofp i64 %0 to float
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ret float %1
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}
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define double @test1u(<2 x i64> %a) {
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entry:
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; CHECK-LABEL: test1u
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; CHECK: xxswapd [[SW:[0-9]+]], 34
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; CHECK: xscvuxddp 1, [[SW]]
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; CHECK-BE-LABEL: test1u
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; CHECK-BE: xscvuxddp 1, 34
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%0 = extractelement <2 x i64> %a, i32 0
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%1 = uitofp i64 %0 to double
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ret double %1
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}
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define double @test2u(<2 x i64> %a) {
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entry:
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; CHECK-LABEL: test2u
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; CHECK: xscvuxddp 1, 34
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; CHECK-BE-LABEL: test2u
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; CHECK-BE: xxswapd [[SW:[0-9]+]], 34
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; CHECK-BE: xscvuxddp 1, [[SW]]
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%0 = extractelement <2 x i64> %a, i32 1
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%1 = uitofp i64 %0 to double
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ret double %1
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}
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define float @test1fu(<2 x i64> %a) {
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entry:
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; CHECK-LABEL: test1fu
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; CHECK: xxswapd [[SW:[0-9]+]], 34
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; CHECK: xscvuxdsp 1, [[SW]]
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; CHECK-BE-LABEL: test1fu
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; CHECK-BE: xscvuxdsp 1, 34
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%0 = extractelement <2 x i64> %a, i32 0
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%1 = uitofp i64 %0 to float
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ret float %1
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}
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define float @test2fu(<2 x i64> %a) {
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entry:
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; CHECK-LABEL: test2fu
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; CHECK: xscvuxdsp 1, 34
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; CHECK-BE-LABEL: test2fu
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; CHECK-BE: xxswapd [[SW:[0-9]+]], 34
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; CHECK-BE: xscvuxdsp 1, [[SW]]
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%0 = extractelement <2 x i64> %a, i32 1
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%1 = uitofp i64 %0 to float
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ret float %1
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}
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define float @conv2fltTesti0(<4 x i32> %a) {
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entry:
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; CHECK-LABEL: conv2fltTesti0
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; CHECK: xxspltw [[SW:[0-9]+]], 34, 3
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; CHECK: xvcvsxwsp [[SW]], [[SW]]
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; CHECK: xscvspdpn 1, [[SW]]
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; CHECK-BE-LABEL: conv2fltTesti0
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; CHECK-BE: xxspltw [[CP:[0-9]+]], 34, 0
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; CHECK-BE: xvcvsxwsp [[CP]], [[CP]]
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; CHECK-BE: xscvspdpn 1, [[CP]]
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%vecext = extractelement <4 x i32> %a, i32 0
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%conv = sitofp i32 %vecext to float
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ret float %conv
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}
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define float @conv2fltTesti1(<4 x i32> %a) {
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entry:
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; CHECK-LABEL: conv2fltTesti1
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; CHECK: xxspltw [[SW:[0-9]+]], 34, 2
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; CHECK: xvcvsxwsp [[SW]], [[SW]]
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; CHECK: xscvspdpn 1, [[SW]]
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; CHECK-BE-LABEL: conv2fltTesti1
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; CHECK-BE: xxspltw [[CP:[0-9]+]], 34, 1
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; CHECK-BE: xvcvsxwsp [[CP]], [[CP]]
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; CHECK-BE: xscvspdpn 1, [[CP]]
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%vecext = extractelement <4 x i32> %a, i32 1
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%conv = sitofp i32 %vecext to float
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ret float %conv
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}
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define float @conv2fltTesti2(<4 x i32> %a) {
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entry:
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; CHECK-LABEL: conv2fltTesti2
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; CHECK: xxspltw [[SW:[0-9]+]], 34, 1
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; CHECK: xvcvsxwsp [[SW]], [[SW]]
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; CHECK: xscvspdpn 1, [[SW]]
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; CHECK-BE-LABEL: conv2fltTesti2
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; CHECK-BE: xxspltw [[CP:[0-9]+]], 34, 2
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; CHECK-BE: xvcvsxwsp [[CP]], [[CP]]
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; CHECK-BE: xscvspdpn 1, [[CP]]
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%vecext = extractelement <4 x i32> %a, i32 2
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%conv = sitofp i32 %vecext to float
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ret float %conv
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}
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define float @conv2fltTesti3(<4 x i32> %a) {
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entry:
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; CHECK-LABEL: conv2fltTesti3
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; CHECK: xxspltw [[SW:[0-9]+]], 34, 0
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; CHECK: xvcvsxwsp [[SW]], [[SW]]
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; CHECK: xscvspdpn 1, [[SW]]
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; CHECK-BE-LABEL: conv2fltTesti3
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; CHECK-BE: xxspltw [[CP:[0-9]+]], 34, 3
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; CHECK-BE: xvcvsxwsp [[CP]], [[CP]]
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; CHECK-BE: xscvspdpn 1, [[CP]]
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%vecext = extractelement <4 x i32> %a, i32 3
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%conv = sitofp i32 %vecext to float
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ret float %conv
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}
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; verify we don't crash for variable elem extract
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define float @conv2fltTestiVar(<4 x i32> %a, i32 zeroext %elem) {
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entry:
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%vecext = extractelement <4 x i32> %a, i32 %elem
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%conv = sitofp i32 %vecext to float
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ret float %conv
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}
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define double @conv2dblTesti0(<4 x i32> %a) {
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entry:
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; CHECK-LABEL: conv2dblTesti0
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; CHECK: xxspltw [[SW:[0-9]+]], 34, 3
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; CHECK: xvcvsxwdp 1, [[SW]]
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; CHECK-BE-LABEL: conv2dblTesti0
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; CHECK-BE: xxspltw [[CP:[0-9]+]], 34, 0
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; CHECK-BE: xvcvsxwdp 1, [[CP]]
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%vecext = extractelement <4 x i32> %a, i32 0
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%conv = sitofp i32 %vecext to double
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ret double %conv
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}
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define double @conv2dblTesti1(<4 x i32> %a) {
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entry:
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; CHECK-LABEL: conv2dblTesti1
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; CHECK: xxspltw [[SW:[0-9]+]], 34, 2
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; CHECK: xvcvsxwdp 1, [[SW]]
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; CHECK-BE-LABEL: conv2dblTesti1
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; CHECK-BE: xxspltw [[CP:[0-9]+]], 34, 1
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; CHECK-BE: xvcvsxwdp 1, [[CP]]
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%vecext = extractelement <4 x i32> %a, i32 1
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%conv = sitofp i32 %vecext to double
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ret double %conv
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}
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define double @conv2dblTesti2(<4 x i32> %a) {
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entry:
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; CHECK-LABEL: conv2dblTesti2
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; CHECK: xxspltw [[SW:[0-9]+]], 34, 1
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; CHECK: xvcvsxwdp 1, [[SW]]
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; CHECK-BE-LABEL: conv2dblTesti2
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; CHECK-BE: xxspltw [[CP:[0-9]+]], 34, 2
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; CHECK-BE: xvcvsxwdp 1, [[CP]]
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%vecext = extractelement <4 x i32> %a, i32 2
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%conv = sitofp i32 %vecext to double
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ret double %conv
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}
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define double @conv2dblTesti3(<4 x i32> %a) {
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entry:
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; CHECK-LABEL: conv2dblTesti3
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; CHECK: xxspltw [[SW:[0-9]+]], 34, 0
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; CHECK: xvcvsxwdp 1, [[SW]]
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; CHECK-BE-LABEL: conv2dblTesti3
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; CHECK-BE: xxspltw [[CP:[0-9]+]], 34, 3
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; CHECK-BE: xvcvsxwdp 1, [[CP]]
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%vecext = extractelement <4 x i32> %a, i32 3
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%conv = sitofp i32 %vecext to double
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ret double %conv
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}
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; verify we don't crash for variable elem extract
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define double @conv2dblTestiVar(<4 x i32> %a, i32 zeroext %elem) {
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entry:
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%vecext = extractelement <4 x i32> %a, i32 %elem
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%conv = sitofp i32 %vecext to double
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ret double %conv
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}
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