RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-22 10:42:39 +01:00
Code Issues Projects Releases Wiki Activity
5ff8f4151c
llvm-mirror/test/CodeGen/PowerPC/sink-down-more-instructions-1.mir
Matt Arsenault cc12b285b6 CodeGen: Print/parse LLTs in MachineMemOperands 
This will currently accept the old number of bytes syntax, and convert
it to a scalar. This should be removed in the near future (I think I
converted all of the tests already, but likely missed a few).

Not sure what the exact syntax and policy should be. We can continue
printing the number of bytes for non-generic instructions to avoid
test churn and only allow non-scalar types for generic instructions.

This will currently print the LLT in parentheses, but accept parsing
the existing integers and implicitly converting to scalar. The
parentheses are a bit ugly, but the parser logic seems unable to deal
without either parentheses or some keyword to indicate the start of a
type.
2021-06-30 16:54:13 -04:00

598 lines
22 KiB
YAML
Raw Blame History

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -o - %s -verify-machineinstrs \
# RUN: -run-pass=machine-sink | FileCheck %s
--- |
; ModuleID = 'sink-down-more-instructions-1.ll'
source_filename = "sink-down-more-instructions-1.c"
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"
; Function Attrs: nofree norecurse nounwind
define dso_local signext i32 @foo(i32 signext %0, i32 signext %1, i32* nocapture readonly %2, i32* nocapture %3, i32 signext %4) local_unnamed_addr #0 {
%6 = icmp sgt i32 %4, 0
br i1 %6, label %7, label %37
7: ; preds = %5
%8 = zext i32 %4 to i64
%9 = icmp eq i32 %4, 1
br i1 %9, label %17, label %10
10: ; preds = %7
%11 = and i64 %8, 4294967294
%scevgep20 = getelementptr i32, i32* %2, i64 -2
%scevgep2021 = bitcast i32* %scevgep20 to i8*
%scevgep22 = getelementptr i32, i32* %3, i64 -2
%scevgep2223 = bitcast i32* %scevgep22 to i8*
%12 = add nsw i64 %11, -2
%13 = lshr i64 %12, 1
%14 = add nuw i64 %13, 1
call void @llvm.set.loop.iterations.i64(i64 %14)
br label %38
15: ; preds = %74
%16 = add nuw i32 %tmp18, 102
br label %17
17: ; preds = %15, %7
%18 = phi i64 [ 0, %7 ], [ %78, %15 ]
%19 = phi i32 [ 100, %7 ], [ %16, %15 ]
%20 = phi i32 [ 0, %7 ], [ %66, %15 ]
%21 = and i64 %8, 1
%22 = icmp eq i64 %21, 0
br i1 %22, label %37, label %23
23: ; preds = %17
%24 = getelementptr inbounds i32, i32* %2, i64 %18
%25 = load i32, i32* %24, align 4, !tbaa !2
%26 = add nsw i32 %25, %20
switch i32 %0, label %30 [
i32 1, label %27
i32 3, label %33
]
27: ; preds = %23
%28 = trunc i64 %18 to i32
%29 = shl i32 %28, 1
br label %33
30: ; preds = %23
%31 = trunc i64 %18 to i32
%32 = urem i32 %31, 30
br label %33
33: ; preds = %30, %27, %23
%34 = phi i32 [ %32, %30 ], [ %29, %27 ], [ %19, %23 ]
%35 = add nsw i32 %34, %26
%36 = getelementptr inbounds i32, i32* %3, i64 %18
store i32 %35, i32* %36, align 4, !tbaa !2
br label %37
37: ; preds = %33, %17, %5
ret i32 undef
38: ; preds = %74, %10
%39 = phi i64 [ 0, %10 ], [ %78, %74 ]
%40 = phi i32 [ 0, %10 ], [ %66, %74 ]
%41 = phi i8* [ %scevgep2021, %10 ], [ %45, %74 ]
%42 = phi i8* [ %scevgep2223, %10 ], [ %43, %74 ]
%43 = getelementptr i8, i8* %42, i64 8
%44 = bitcast i8* %43 to i32*
%45 = getelementptr i8, i8* %41, i64 8
%46 = bitcast i8* %45 to i32*
%lsr19 = trunc i64 %39 to i32
%47 = udiv i32 %lsr19, 30
%48 = mul nsw i32 %47, -30
%49 = zext i32 %48 to i64
%50 = add nuw nsw i64 %49, 1
%51 = load i32, i32* %46, align 4, !tbaa !2
%52 = add nsw i32 %51, %40
switch i32 %0, label %58 [
i32 1, label %53
i32 3, label %56
]
53: ; preds = %38
%54 = trunc i64 %39 to i32
%55 = shl i32 %54, 1
br label %60
56: ; preds = %38
%57 = add nuw nsw i32 %lsr19, 100
br label %60
58: ; preds = %38
%59 = add i64 %39, %49
%tmp15 = trunc i64 %59 to i32
br label %60
60: ; preds = %58, %56, %53
%61 = phi i32 [ %tmp15, %58 ], [ %57, %56 ], [ %55, %53 ]
%62 = add nsw i32 %61, %52
store i32 %62, i32* %44, align 4, !tbaa !2
%63 = or i64 %39, 1
%64 = getelementptr i8, i8* %45, i64 4
%uglygep1112.cast = bitcast i8* %64 to i32*
%65 = load i32, i32* %uglygep1112.cast, align 4, !tbaa !2
%66 = add nsw i32 %65, %52
switch i32 %0, label %72 [
i32 1, label %69
i32 3, label %67
]
67: ; preds = %60
%68 = add nuw nsw i32 %lsr19, 101
br label %74
69: ; preds = %60
%70 = trunc i64 %63 to i32
%71 = shl i32 %70, 1
br label %74
72: ; preds = %60
%73 = add i64 %39, %50
%tmp = trunc i64 %73 to i32
br label %74
74: ; preds = %72, %69, %67
%75 = phi i32 [ %tmp, %72 ], [ %68, %67 ], [ %71, %69 ]
%76 = add nsw i32 %75, %66
%77 = getelementptr i8, i8* %43, i64 4
%uglygep78.cast = bitcast i8* %77 to i32*
store i32 %76, i32* %uglygep78.cast, align 4, !tbaa !2
%78 = add nuw nsw i64 %39, 2
%79 = add i64 %78, -2
%tmp18 = trunc i64 %79 to i32
%80 = call i1 @llvm.loop.decrement.i64(i64 1)
br i1 %80, label %38, label %15
}
; Function Attrs: noduplicate nounwind
declare void @llvm.set.loop.iterations.i64(i64) #1
; Function Attrs: noduplicate nounwind
declare i1 @llvm.loop.decrement.i64(i64) #1
attributes #0 = { nofree norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector,-spe" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { noduplicate nounwind }
!llvm.module.flags = !{!0}
!llvm.ident = !{!1}
!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{!"clang version 12.0.0"}
!2 = !{!3, !3, i64 0}
!3 = !{!"int", !4, i64 0}
!4 = !{!"omnipotent char", !5, i64 0}
!5 = !{!"Simple C/C++ TBAA"}
...
---
name: foo
alignment: 16
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc }
- { id: 1, class: g8rc }
- { id: 2, class: g8rc }
- { id: 3, class: gprc }
- { id: 4, class: g8rc }
- { id: 5, class: gprc }
- { id: 6, class: gprc }
- { id: 7, class: gprc }
- { id: 8, class: gprc_and_gprc_nor0 }
- { id: 9, class: gprc }
- { id: 10, class: gprc }
- { id: 11, class: g8rc_and_g8rc_nox0 }
- { id: 12, class: gprc }
- { id: 13, class: g8rc_and_g8rc_nox0 }
- { id: 14, class: g8rc_and_g8rc_nox0 }
- { id: 15, class: g8rc_and_g8rc_nox0 }
- { id: 16, class: g8rc_and_g8rc_nox0 }
- { id: 17, class: g8rc_and_g8rc_nox0 }
- { id: 18, class: gprc_and_gprc_nor0 }
- { id: 19, class: g8rc }
- { id: 20, class: g8rc }
- { id: 21, class: gprc }
- { id: 22, class: gprc_and_gprc_nor0 }
- { id: 23, class: gprc }
- { id: 24, class: gprc }
- { id: 25, class: gprc }
- { id: 26, class: g8rc }
- { id: 27, class: gprc }
- { id: 28, class: gprc }
- { id: 29, class: gprc }
- { id: 30, class: gprc }
- { id: 31, class: gprc }
- { id: 32, class: g8rc }
- { id: 33, class: gprc_and_gprc_nor0 }
- { id: 34, class: g8rc }
- { id: 35, class: g8rc }
- { id: 36, class: g8rc_and_g8rc_nox0 }
- { id: 37, class: g8rc_and_g8rc_nox0 }
- { id: 38, class: g8rc }
- { id: 39, class: gprc }
- { id: 40, class: gprc }
- { id: 41, class: crrc }
- { id: 42, class: g8rc }
- { id: 43, class: gprc }
- { id: 44, class: gprc }
- { id: 45, class: g8rc }
- { id: 46, class: g8rc }
- { id: 47, class: crrc }
- { id: 48, class: g8rc }
- { id: 49, class: gprc }
- { id: 50, class: g8rc_and_g8rc_nox0 }
- { id: 51, class: g8rc }
- { id: 52, class: g8rc_and_g8rc_nox0 }
- { id: 53, class: g8rc }
- { id: 54, class: gprc }
- { id: 55, class: g8rc_and_g8rc_nox0 }
- { id: 56, class: gprc }
- { id: 57, class: gprc }
- { id: 58, class: gprc }
- { id: 59, class: gprc }
- { id: 60, class: gprc }
- { id: 61, class: g8rc }
- { id: 62, class: g8rc }
- { id: 63, class: crrc }
- { id: 64, class: crrc }
- { id: 65, class: gprc }
- { id: 66, class: g8rc }
- { id: 67, class: gprc }
- { id: 68, class: gprc }
- { id: 69, class: crrc }
- { id: 70, class: crrc }
- { id: 71, class: gprc }
- { id: 72, class: g8rc }
- { id: 73, class: gprc }
- { id: 74, class: gprc_and_gprc_nor0 }
- { id: 75, class: crbitrc }
- { id: 76, class: g8rc }
- { id: 77, class: gprc }
- { id: 78, class: crrc }
- { id: 79, class: crrc }
- { id: 80, class: gprc }
- { id: 81, class: gprc }
- { id: 82, class: gprc }
- { id: 83, class: gprc }
- { id: 84, class: gprc }
- { id: 85, class: gprc }
- { id: 86, class: gprc }
- { id: 87, class: gprc }
- { id: 88, class: g8rc }
- { id: 89, class: g8rc }
- { id: 90, class: g8rc }
- { id: 91, class: gprc }
- { id: 92, class: gprc_nor0 }
- { id: 93, class: gprc }
- { id: 94, class: gprc_nor0 }
- { id: 95, class: crrc }
liveins:
- { reg: '$x3', virtual-reg: '%34' }
- { reg: '$x5', virtual-reg: '%36' }
- { reg: '$x6', virtual-reg: '%37' }
- { reg: '$x7', virtual-reg: '%38' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: foo
; CHECK: bb.0 (%ir-block.5):
; CHECK: successors: %bb.1(0x50000000), %bb.8(0x30000000)
; CHECK: liveins: $x3, $x5, $x6, $x7
; CHECK: [[COPY:%[0-9]+]]:g8rc = COPY $x7
; CHECK: [[COPY1:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x6
; CHECK: [[COPY2:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x5
; CHECK: [[COPY3:%[0-9]+]]:g8rc = COPY $x3
; CHECK: [[COPY4:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
; CHECK: [[CMPWI:%[0-9]+]]:crrc = CMPWI [[COPY4]], 1
; CHECK: BCC 12, killed [[CMPWI]], %bb.8
; CHECK: B %bb.1
; CHECK: bb.1 (%ir-block.7):
; CHECK: successors: %bb.18(0x40000000), %bb.2(0x40000000)
; CHECK: [[COPY5:%[0-9]+]]:gprc = COPY [[COPY3]].sub_32
; CHECK: [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF]], [[COPY4]], %subreg.sub_32
; CHECK: [[RLDICL:%[0-9]+]]:g8rc = RLDICL killed [[INSERT_SUBREG]], 0, 32
; CHECK: [[CMPLWI:%[0-9]+]]:crrc = CMPLWI [[COPY4]], 1
; CHECK: [[CMPLWI1:%[0-9]+]]:crrc = CMPLWI [[COPY5]], 3
; CHECK: BCC 68, killed [[CMPLWI]], %bb.2
; CHECK: bb.18:
; CHECK: successors: %bb.4(0x80000000)
; CHECK: [[LI:%[0-9]+]]:gprc = LI 0
; CHECK: [[LI1:%[0-9]+]]:gprc = LI 100
; CHECK: [[LI8_:%[0-9]+]]:g8rc = LI8 0
; CHECK: B %bb.4
; CHECK: bb.2 (%ir-block.10):
; CHECK: successors: %bb.9(0x80000000)
; CHECK: [[RLWINM8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = RLWINM8 [[RLDICL]], 0, 0, 30
; CHECK: [[ADDI8_:%[0-9]+]]:g8rc = ADDI8 [[COPY2]], -8
; CHECK: [[ADDI8_1:%[0-9]+]]:g8rc = ADDI8 [[COPY1]], -8
; CHECK: [[ADDI8_2:%[0-9]+]]:g8rc = nsw ADDI8 killed [[RLWINM8_]], -2
; CHECK: [[RLDICL1:%[0-9]+]]:g8rc_and_g8rc_nox0 = RLDICL [[ADDI8_2]], 63, 1
; CHECK: [[ADDI8_3:%[0-9]+]]:g8rc = nuw ADDI8 killed [[RLDICL1]], 1
; CHECK: MTCTR8loop killed [[ADDI8_3]], implicit-def dead $ctr8
; CHECK: [[LI2:%[0-9]+]]:gprc = LI 0
; CHECK: [[LI8_1:%[0-9]+]]:g8rc = LI8 0
; CHECK: [[LIS:%[0-9]+]]:gprc = LIS 34952
; CHECK: [[ORI:%[0-9]+]]:gprc = ORI [[LIS]], 34953
; CHECK: [[DEF1:%[0-9]+]]:g8rc = IMPLICIT_DEF
; CHECK: [[CMPLWI2:%[0-9]+]]:crrc = CMPLWI [[COPY5]], 1
; CHECK: B %bb.9
; CHECK: bb.3 (%ir-block.15):
; CHECK: successors: %bb.4(0x80000000)
; CHECK: [[COPY6:%[0-9]+]]:gprc_and_gprc_nor0 = COPY %32.sub_32
; CHECK: [[ADDI:%[0-9]+]]:gprc_and_gprc_nor0 = ADDI [[COPY6]], -2
; CHECK: [[ADDI1:%[0-9]+]]:gprc = nuw ADDI [[ADDI]], 102
; CHECK: bb.4 (%ir-block.17):
; CHECK: successors: %bb.8(0x40000000), %bb.5(0x40000000)
; CHECK: [[PHI:%[0-9]+]]:g8rc = PHI [[LI8_]], %bb.18, %32, %bb.3
; CHECK: [[PHI1:%[0-9]+]]:gprc = PHI [[LI1]], %bb.18, [[ADDI1]], %bb.3
; CHECK: [[PHI2:%[0-9]+]]:gprc = PHI [[LI]], %bb.18, %27, %bb.3
; CHECK: [[ANDI8_rec:%[0-9]+]]:g8rc = ANDI8_rec [[RLDICL]], 1, implicit-def $cr0
; CHECK: [[COPY7:%[0-9]+]]:crbitrc = COPY $cr0gt
; CHECK: BCn killed [[COPY7]], %bb.8
; CHECK: B %bb.5
; CHECK: bb.5 (%ir-block.23):
; CHECK: successors: %bb.7(0x2aaaaaab), %bb.6(0x55555555)
; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[PHI]], 2, 61
; CHECK: [[LWZX:%[0-9]+]]:gprc = LWZX [[COPY2]], [[RLDICR]] :: (load (s32) from %ir.24, !tbaa !2)
; CHECK: [[ADD4_:%[0-9]+]]:gprc = nsw ADD4 killed [[LWZX]], [[PHI2]]
; CHECK: BCC 76, [[CMPLWI1]], %bb.7
; CHECK: B %bb.6
; CHECK: bb.6 (%ir-block.23):
; CHECK: successors: %bb.7(0x80000000)
; CHECK: [[CMPLWI3:%[0-9]+]]:crrc = CMPLWI [[COPY5]], 1
; CHECK: [[COPY8:%[0-9]+]]:gprc = COPY [[PHI]].sub_32
; CHECK: [[LIS1:%[0-9]+]]:gprc = LIS 34952
; CHECK: [[ORI1:%[0-9]+]]:gprc = ORI killed [[LIS1]], 34953
; CHECK: [[MULHWU:%[0-9]+]]:gprc = MULHWU [[COPY8]], killed [[ORI1]]
; CHECK: [[RLWINM:%[0-9]+]]:gprc = RLWINM [[MULHWU]], 28, 4, 31
; CHECK: [[MULLI:%[0-9]+]]:gprc = MULLI killed [[RLWINM]], 30
; CHECK: [[SUBF:%[0-9]+]]:gprc = SUBF killed [[MULLI]], [[COPY8]]
; CHECK: [[COPY9:%[0-9]+]]:gprc = COPY [[PHI]].sub_32
; CHECK: [[RLWINM1:%[0-9]+]]:gprc_and_gprc_nor0 = RLWINM [[COPY9]], 1, 0, 30
; CHECK: [[ISEL:%[0-9]+]]:gprc = ISEL [[RLWINM1]], [[SUBF]], [[CMPLWI3]].sub_eq
; CHECK: B %bb.7
; CHECK: bb.7 (%ir-block.33):
; CHECK: successors: %bb.8(0x80000000)
; CHECK: [[PHI3:%[0-9]+]]:gprc = PHI [[PHI1]], %bb.5, [[ISEL]], %bb.6
; CHECK: [[ADD4_1:%[0-9]+]]:gprc = nsw ADD4 [[PHI3]], [[ADD4_]]
; CHECK: STWX killed [[ADD4_1]], [[COPY1]], [[RLDICR]] :: (store (s32) into %ir.36, !tbaa !2)
; CHECK: bb.8 (%ir-block.37):
; CHECK: [[LI8_2:%[0-9]+]]:g8rc = LI8 0
; CHECK: $x3 = COPY [[LI8_2]]
; CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3
; CHECK: bb.9 (%ir-block.38):
; CHECK: successors: %bb.11(0x2aaaaaab), %bb.10(0x55555555)
; CHECK: [[PHI4:%[0-9]+]]:g8rc_and_g8rc_nox0 = PHI [[LI8_1]], %bb.2, %32, %bb.17
; CHECK: [[PHI5:%[0-9]+]]:gprc = PHI [[LI2]], %bb.2, %27, %bb.17
; CHECK: [[PHI6:%[0-9]+]]:g8rc_and_g8rc_nox0 = PHI [[ADDI8_]], %bb.2, %55, %bb.17
; CHECK: [[PHI7:%[0-9]+]]:g8rc_and_g8rc_nox0 = PHI [[ADDI8_1]], %bb.2, %15, %bb.17
; CHECK: [[COPY10:%[0-9]+]]:gprc_and_gprc_nor0 = COPY [[PHI4]].sub_32
; CHECK: [[MULHWU1:%[0-9]+]]:gprc = MULHWU [[COPY10]], [[ORI]]
; CHECK: [[RLWINM2:%[0-9]+]]:gprc = RLWINM [[MULHWU1]], 28, 4, 31
; CHECK: [[MULLI1:%[0-9]+]]:gprc = nsw MULLI killed [[RLWINM2]], -30
; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF1]], killed [[MULLI1]], %subreg.sub_32
; CHECK: [[RLDICL2:%[0-9]+]]:g8rc = RLDICL killed [[INSERT_SUBREG1]], 0, 32
; CHECK: BCC 76, [[CMPLWI1]], %bb.11
; CHECK: B %bb.10
; CHECK: bb.10 (%ir-block.38):
; CHECK: successors: %bb.12(0x80000000)
; CHECK: [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[PHI4]], [[RLDICL2]]
; CHECK: [[COPY11:%[0-9]+]]:gprc = COPY [[ADD8_]].sub_32
; CHECK: [[COPY12:%[0-9]+]]:gprc = COPY [[PHI4]].sub_32
; CHECK: [[RLWINM3:%[0-9]+]]:gprc_and_gprc_nor0 = RLWINM [[COPY12]], 1, 0, 30
; CHECK: [[ISEL1:%[0-9]+]]:gprc = ISEL [[RLWINM3]], [[COPY11]], [[CMPLWI2]].sub_eq
; CHECK: B %bb.12
; CHECK: bb.11 (%ir-block.56):
; CHECK: successors: %bb.12(0x80000000)
; CHECK: [[ADDI2:%[0-9]+]]:gprc = nuw nsw ADDI [[COPY10]], 100
; CHECK: B %bb.12
; CHECK: bb.12 (%ir-block.60):
; CHECK: successors: %bb.15(0x2aaaaaab), %bb.13(0x55555555)
; CHECK: [[PHI8:%[0-9]+]]:gprc = PHI [[ADDI2]], %bb.11, [[ISEL1]], %bb.10
; CHECK: [[ADDI8_4:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[PHI7]], 8
; CHECK: [[LWZU:%[0-9]+]]:gprc, [[LWZU1:%[0-9]+]]:g8rc_and_g8rc_nox0 = LWZU 8, [[PHI6]] :: (load (s32) from %ir.46, !tbaa !2)
; CHECK: [[ADD4_2:%[0-9]+]]:gprc = nsw ADD4 [[LWZU]], [[PHI5]]
; CHECK: [[ADD4_3:%[0-9]+]]:gprc = nsw ADD4 [[PHI8]], [[ADD4_2]]
; CHECK: STW killed [[ADD4_3]], 0, [[ADDI8_4]] :: (store (s32) into %ir.44, !tbaa !2)
; CHECK: [[LWZ:%[0-9]+]]:gprc = LWZ 4, [[LWZU1]] :: (load (s32) from %ir.uglygep1112.cast, !tbaa !2)
; CHECK: BCC 76, [[CMPLWI2]], %bb.15
; CHECK: B %bb.13
; CHECK: bb.13 (%ir-block.60):
; CHECK: successors: %bb.14(0x40000001), %bb.16(0x3fffffff)
; CHECK: BCC 68, [[CMPLWI1]], %bb.16
; CHECK: B %bb.14
; CHECK: bb.14 (%ir-block.67):
; CHECK: successors: %bb.17(0x80000000)
; CHECK: [[ADDI3:%[0-9]+]]:gprc = nuw nsw ADDI [[COPY10]], 101
; CHECK: B %bb.17
; CHECK: bb.15 (%ir-block.69):
; CHECK: successors: %bb.17(0x80000000)
; CHECK: [[ORI8_:%[0-9]+]]:g8rc = ORI8 [[PHI4]], 1
; CHECK: [[COPY13:%[0-9]+]]:gprc = COPY [[ORI8_]].sub_32
; CHECK: [[RLWINM4:%[0-9]+]]:gprc = RLWINM [[COPY13]], 1, 0, 30
; CHECK: B %bb.17
; CHECK: bb.16 (%ir-block.72):
; CHECK: successors: %bb.17(0x80000000)
; CHECK: [[ORI8_1:%[0-9]+]]:g8rc = ORI8 [[RLDICL2]], 1
; CHECK: [[ADD8_1:%[0-9]+]]:g8rc = ADD8 [[PHI4]], [[ORI8_1]]
; CHECK: [[COPY14:%[0-9]+]]:gprc = COPY [[ADD8_1]].sub_32
; CHECK: bb.17 (%ir-block.74):
; CHECK: successors: %bb.9(0x7c000000), %bb.3(0x04000000)
; CHECK: [[PHI9:%[0-9]+]]:gprc = PHI [[ADDI3]], %bb.14, [[RLWINM4]], %bb.15, [[COPY14]], %bb.16
; CHECK: [[COPY15:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY [[ADDI8_4]]
; CHECK: [[ADD4_4:%[0-9]+]]:gprc = nsw ADD4 [[LWZ]], [[ADD4_2]]
; CHECK: [[ADD4_5:%[0-9]+]]:gprc = nsw ADD4 [[PHI9]], [[ADD4_4]]
; CHECK: STW killed [[ADD4_5]], 4, [[COPY15]] :: (store (s32) into %ir.uglygep78.cast, !tbaa !2)
; CHECK: [[ADDI8_5:%[0-9]+]]:g8rc = nuw nsw ADDI8 [[PHI4]], 2
; CHECK: BDNZ8 %bb.9, implicit-def dead $ctr8, implicit $ctr8
; CHECK: B %bb.3
bb.0 (%ir-block.5):
successors: %bb.1(0x50000000), %bb.9(0x30000000)
liveins: $x3, $x5, $x6, $x7
%38:g8rc = COPY $x7
%37:g8rc_and_g8rc_nox0 = COPY $x6
%36:g8rc_and_g8rc_nox0 = COPY $x5
%34:g8rc = COPY $x3
%39:gprc = COPY %34.sub_32
%40:gprc = COPY %38.sub_32
%41:crrc = CMPWI %40, 1
BCC 12, killed %41, %bb.9
B %bb.1
bb.1 (%ir-block.7):
%46:g8rc = IMPLICIT_DEF
%45:g8rc = INSERT_SUBREG %46, %40, %subreg.sub_32
%0:g8rc = RLDICL killed %45, 0, 32
%44:gprc = LI 0
%43:gprc = LI 100
%42:g8rc = LI8 0
%47:crrc = CMPLWI %40, 1
%95:crrc = CMPLWI %39, 3
BCC 76, killed %47, %bb.4
B %bb.2
bb.2 (%ir-block.10):
%50:g8rc_and_g8rc_nox0 = RLWINM8 %0, 0, 0, 30
%1:g8rc = ADDI8 %36, -8
%2:g8rc = ADDI8 %37, -8
%51:g8rc = nsw ADDI8 killed %50, -2
%52:g8rc_and_g8rc_nox0 = RLDICL %51, 63, 1
%53:g8rc = nuw ADDI8 killed %52, 1
MTCTR8loop killed %53, implicit-def dead $ctr8
%49:gprc = LI 0
%48:g8rc = LI8 0
%56:gprc = LIS 34952
%57:gprc = ORI %56, 34953
%62:g8rc = IMPLICIT_DEF
%69:crrc = CMPLWI %39, 1
B %bb.10
bb.3 (%ir-block.15):
%3:gprc = nuw ADDI %33, 102
bb.4 (%ir-block.17):
%4:g8rc = PHI %42, %bb.1, %32, %bb.3
%5:gprc = PHI %43, %bb.1, %3, %bb.3
%6:gprc = PHI %44, %bb.1, %27, %bb.3
%90:g8rc = ANDI8_rec %0, 1, implicit-def $cr0
%75:crbitrc = COPY $cr0gt
BCn killed %75, %bb.9
B %bb.5
bb.5 (%ir-block.23):
successors: %bb.8(0x2aaaaaab), %bb.21(0x55555555)
%76:g8rc = RLDICR %4, 2, 61
%77:gprc = LWZX %36, %76 :: (load (s32) from %ir.24, !tbaa !2)
%7:gprc = nsw ADD4 killed %77, %6
BCC 76, %95, %bb.8
B %bb.21
bb.21 (%ir-block.23):
%79:crrc = CMPLWI %39, 1
%81:gprc = COPY %4.sub_32
%82:gprc = LIS 34952
%83:gprc = ORI killed %82, 34953
%84:gprc = MULHWU %81, killed %83
%85:gprc = RLWINM %84, 28, 4, 31
%86:gprc = MULLI killed %85, 30
%9:gprc = SUBF killed %86, %81
%80:gprc = COPY %4.sub_32
%8:gprc_and_gprc_nor0 = RLWINM %80, 1, 0, 30
%91:gprc = ISEL %8, %9, %79.sub_eq
B %bb.8
bb.8 (%ir-block.33):
%10:gprc = PHI %5, %bb.5, %91, %bb.21
%87:gprc = nsw ADD4 %10, %7
STWX killed %87, %37, %76 :: (store (s32) into %ir.36, !tbaa !2)
bb.9 (%ir-block.37):
%89:g8rc = LI8 0
$x3 = COPY %89
BLR8 implicit $lr8, implicit $rm, implicit $x3
bb.10 (%ir-block.38):
successors: %bb.12(0x2aaaaaab), %bb.19(0x55555555)
%11:g8rc_and_g8rc_nox0 = PHI %48, %bb.2, %32, %bb.18
%12:gprc = PHI %49, %bb.2, %27, %bb.18
%13:g8rc_and_g8rc_nox0 = PHI %1, %bb.2, %17, %bb.18
%14:g8rc_and_g8rc_nox0 = PHI %2, %bb.2, %15, %bb.18
%16:g8rc_and_g8rc_nox0 = ADDI8 %14, 8
%15:g8rc_and_g8rc_nox0 = COPY %16
%54:gprc, %55:g8rc_and_g8rc_nox0 = LWZU 8, %13 :: (load (s32) from %ir.46, !tbaa !2)
%17:g8rc_and_g8rc_nox0 = COPY %55
%18:gprc_and_gprc_nor0 = COPY %11.sub_32
%58:gprc = MULHWU %18, %57
%59:gprc = RLWINM %58, 28, 4, 31
%60:gprc = nsw MULLI killed %59, -30
%61:g8rc = INSERT_SUBREG %62, killed %60, %subreg.sub_32
%19:g8rc = RLDICL killed %61, 0, 32
%20:g8rc = ORI8 %19, 1
%21:gprc = nsw ADD4 killed %54, %12
BCC 76, %95, %bb.12
B %bb.19
bb.19 (%ir-block.38):
%66:g8rc = ADD8 %11, %19
%24:gprc = COPY %66.sub_32
%65:gprc = COPY %11.sub_32
%22:gprc_and_gprc_nor0 = RLWINM %65, 1, 0, 30
%93:gprc = ISEL %22, %24, %69.sub_eq
B %bb.14
bb.12 (%ir-block.56):
%23:gprc = nuw nsw ADDI %18, 100
B %bb.14
bb.14 (%ir-block.60):
successors: %bb.16(0x2aaaaaab), %bb.20(0x55555555)
%25:gprc = PHI %23, %bb.12, %93, %bb.19
%67:gprc = nsw ADD4 %25, %21
STW killed %67, 0, %16 :: (store (s32) into %ir.44, !tbaa !2)
%26:g8rc = ORI8 %11, 1
%68:gprc = LWZ 4, %17 :: (load (s32) from %ir.uglygep1112.cast, !tbaa !2)
%27:gprc = nsw ADD4 killed %68, %21
BCC 76, %69, %bb.16
B %bb.20
bb.20 (%ir-block.60):
successors: %bb.15(0x40000001), %bb.17(0x3fffffff)
BCC 68, %95, %bb.17
B %bb.15
bb.15 (%ir-block.67):
%28:gprc = nuw nsw ADDI %18, 101
B %bb.18
bb.16 (%ir-block.69):
%71:gprc = COPY %26.sub_32
%29:gprc = RLWINM %71, 1, 0, 30
B %bb.18
bb.17 (%ir-block.72):
%72:g8rc = ADD8 %11, %20
%30:gprc = COPY %72.sub_32
bb.18 (%ir-block.74):
successors: %bb.10(0x7c000000), %bb.3(0x04000000)
%31:gprc = PHI %28, %bb.15, %29, %bb.16, %30, %bb.17
%73:gprc = nsw ADD4 %31, %27
STW killed %73, 4, %15 :: (store (s32) into %ir.uglygep78.cast, !tbaa !2)
%32:g8rc = nuw nsw ADDI8 %11, 2
%74:gprc_and_gprc_nor0 = COPY %32.sub_32
%33:gprc_and_gprc_nor0 = ADDI killed %74, -2
BDNZ8 %bb.10, implicit-def dead $ctr8, implicit $ctr8
B %bb.3
...
Reference in New Issue View Git Blame Copy Permalink