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The stack frame update code does not take into consideration spilling to registers for callee saved registers. The option -ppc-enable-pe-vector-spills turns on spilling to registers for callee saved registers and may expose a bug in the code that moves a stack frame pointer update instruction. Reviewed By: nemanjai, #powerpc Differential Revision: https://reviews.llvm.org/D101366
42 lines
1019 B
YAML
42 lines
1019 B
YAML
# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 \
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# RUN: -start-before=prologepilog -ppc-enable-pe-vector-spills \
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# RUN: -ppc-asm-full-reg-names -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: MixedSpill
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alignment: 16
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tracksRegLiveness: true
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liveins:
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body: |
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bb.0.entry:
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$r14 = IMPLICIT_DEF
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$f14 = IMPLICIT_DEF
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$lr8 = IMPLICIT_DEF
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BLR8 implicit undef $lr8, implicit undef $rm
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# CHECK-LABEL: MixedSpill
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# CHECK: stdu r1, -176(r1)
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# CHECK: stfd f14, 32(r1)
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# CHECK: mtvsrd vs32, r14
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# CHECK: lfd f14, 32(r1)
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# CHECK: addi r1, r1, 176
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# CHECK: blr
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...
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---
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name: NoStackUpdate
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alignment: 16
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tracksRegLiveness: true
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liveins:
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body: |
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bb.0.entry:
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$r14 = IMPLICIT_DEF
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$f14 = IMPLICIT_DEF
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BLR8 implicit undef $lr8, implicit undef $rm
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# CHECK-LABEL: NoStackUpdate
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# CHECK-NOT: stdu
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# CHECK: mtvsrd vs32, r14
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# CHECK: mfvsrd r14, vs32
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# CHECK: blr
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...
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