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https://github.com/RPCS3/llvm-mirror.git
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d49cb60862
Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
85 lines
2.3 KiB
YAML
85 lines
2.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
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--- |
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define void @test_ashr() { ret void }
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define void @test_ashr_i1() { ret void }
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...
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---
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name: test_ashr
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alignment: 16
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legalized: false
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regBankSelected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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- { id: 2, class: _, preferred-register: '' }
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- { id: 3, class: _, preferred-register: '' }
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- { id: 4, class: _, preferred-register: '' }
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- { id: 5, class: _, preferred-register: '' }
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- { id: 6, class: _, preferred-register: '' }
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- { id: 7, class: _, preferred-register: '' }
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- { id: 8, class: _, preferred-register: '' }
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- { id: 9, class: _, preferred-register: '' }
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- { id: 10, class: _, preferred-register: '' }
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- { id: 11, class: _, preferred-register: '' }
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body: |
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bb.1 (%ir-block.0):
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liveins: $rdi, $rsi
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; CHECK-LABEL: name: test_ashr
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; CHECK: liveins: $rdi, $rsi
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
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; CHECK: RET 0
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%0(s64) = COPY $rdi
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%1(s64) = COPY $rsi
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%2(s64) = G_ASHR %0, %1
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%3(s32) = G_TRUNC %0
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%4(s32) = G_TRUNC %1
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%5(s32) = G_ASHR %3, %4
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%6(s16) = G_TRUNC %0
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%7(s16) = G_TRUNC %1
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%8(s16) = G_ASHR %6, %7
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%9(s8) = G_TRUNC %0
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%10(s8) = G_TRUNC %1
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%11(s8) = G_ASHR %9, %10
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RET 0
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...
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---
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name: test_ashr_i1
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alignment: 16
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legalized: false
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regBankSelected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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- { id: 2, class: _, preferred-register: '' }
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- { id: 3, class: _, preferred-register: '' }
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- { id: 4, class: _, preferred-register: '' }
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body: |
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bb.1 (%ir-block.0):
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liveins: $rdi, $rsi
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; CHECK-LABEL: name: test_ashr_i1
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; CHECK: liveins: $rdi, $rsi
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
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; CHECK: RET 0
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%0(s64) = COPY $rdi
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%1(s64) = COPY $rsi
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%2(s1) = G_TRUNC %0
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%3(s1) = G_TRUNC %1
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%4(s1) = G_ASHR %2, %3
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RET 0
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...
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