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llvm-mirror/test/CodeGen/X86/GlobalISel/legalize-ashr-scalar.mir
Guillaume Chatelet d49cb60862 [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing
Summary:
This catches malformed mir files which specify alignment as log2 instead of pow2.
See https://reviews.llvm.org/D65945 for reference,

This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67433

llvm-svn: 371608
2019-09-11 11:16:48 +00:00

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2.3 KiB
YAML

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
--- |
define void @test_ashr() { ret void }
define void @test_ashr_i1() { ret void }
...
---
name: test_ashr
alignment: 16
legalized: false
regBankSelected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
- { id: 2, class: _, preferred-register: '' }
- { id: 3, class: _, preferred-register: '' }
- { id: 4, class: _, preferred-register: '' }
- { id: 5, class: _, preferred-register: '' }
- { id: 6, class: _, preferred-register: '' }
- { id: 7, class: _, preferred-register: '' }
- { id: 8, class: _, preferred-register: '' }
- { id: 9, class: _, preferred-register: '' }
- { id: 10, class: _, preferred-register: '' }
- { id: 11, class: _, preferred-register: '' }
body: |
bb.1 (%ir-block.0):
liveins: $rdi, $rsi
; CHECK-LABEL: name: test_ashr
; CHECK: liveins: $rdi, $rsi
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
; CHECK: RET 0
%0(s64) = COPY $rdi
%1(s64) = COPY $rsi
%2(s64) = G_ASHR %0, %1
%3(s32) = G_TRUNC %0
%4(s32) = G_TRUNC %1
%5(s32) = G_ASHR %3, %4
%6(s16) = G_TRUNC %0
%7(s16) = G_TRUNC %1
%8(s16) = G_ASHR %6, %7
%9(s8) = G_TRUNC %0
%10(s8) = G_TRUNC %1
%11(s8) = G_ASHR %9, %10
RET 0
...
---
name: test_ashr_i1
alignment: 16
legalized: false
regBankSelected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
- { id: 2, class: _, preferred-register: '' }
- { id: 3, class: _, preferred-register: '' }
- { id: 4, class: _, preferred-register: '' }
body: |
bb.1 (%ir-block.0):
liveins: $rdi, $rsi
; CHECK-LABEL: name: test_ashr_i1
; CHECK: liveins: $rdi, $rsi
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
; CHECK: RET 0
%0(s64) = COPY $rdi
%1(s64) = COPY $rsi
%2(s1) = G_TRUNC %0
%3(s1) = G_TRUNC %1
%4(s1) = G_ASHR %2, %3
RET 0
...