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https://github.com/RPCS3/llvm-mirror.git
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d49cb60862
Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
64 lines
1.9 KiB
YAML
64 lines
1.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+bmi -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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#
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# Test that rules where multiple operands must be the same operand successfully
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# match. Also test that the rules do not match when they're not the same
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# operand.
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#
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# This test covers the case when OtherInsnID and OtherOpIdx are different in a
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# GIM_CheckIsSameOperand.
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---
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name: test_blsi32rr
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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# G_SUB and G_AND both use %0 so we should match this.
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body: |
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bb.1:
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liveins: $edi
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; CHECK-LABEL: name: test_blsi32rr
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[BLSI32rr:%[0-9]+]]:gr32 = BLSI32rr [[COPY]], implicit-def $eflags
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; CHECK: $edi = COPY [[BLSI32rr]]
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%0(s32) = COPY $edi
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%1(s32) = G_CONSTANT i32 0
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%2(s32) = G_SUB %1, %0
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%3(s32) = G_AND %2, %0
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$edi = COPY %3
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...
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---
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name: test_blsi32rr_nomatch
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alignment: 16
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legalized: true
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regBankSelected: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: gpr }
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- { id: 3, class: gpr }
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# G_SUB and G_AND use different operands so we shouldn't match this.
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body: |
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bb.1:
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liveins: $edi
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; CHECK-LABEL: name: test_blsi32rr_nomatch
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
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; CHECK: [[SUB32ri:%[0-9]+]]:gr32 = SUB32ri8 [[MOV32r0_]], 0, implicit-def $eflags
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; CHECK: [[AND32rr:%[0-9]+]]:gr32 = AND32rr [[SUB32ri]], [[COPY]], implicit-def $eflags
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; CHECK: $edi = COPY [[AND32rr]]
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%0(s32) = COPY $edi
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%1(s32) = G_CONSTANT i32 0
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%2(s32) = G_SUB %1, %1
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%3(s32) = G_AND %2, %0
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$edi = COPY %3
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...
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