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llvm-mirror/test/CodeGen/X86/fast-isel-ret-ext.ll
Matt Arsenault 5fe7f3e187 RegAllocFast: Improve hinting heuristic
Trace through multiple COPYs when looking for a physreg source. Add
hinting for vregs that will be copied into physregs (we only hinted
for vregs getting copied to a physreg previously).  Give hinted a
register a bonus when deciding which value to spill.  This is part of
my rewrite regallocfast series. In fact this one doesn't even have an
effect unless you also flip the allocation to happen from back to
front of a basic block. Nonetheless it helps to split this up to ease
review of D52010

Patch by Matthias Braun

llvm-svn: 360887
2019-05-16 12:50:39 +00:00

39 lines
933 B
LLVM

; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple i686-apple-darwin10 | FileCheck %s
; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple x86_64-apple-darwin10 | FileCheck %s
define zeroext i8 @test1(i32 %y) nounwind {
%conv = trunc i32 %y to i8
ret i8 %conv
; CHECK-LABEL: test1:
; CHECK: movzbl {{.*}}, %eax
}
define signext i8 @test2(i32 %y) nounwind {
%conv = trunc i32 %y to i8
ret i8 %conv
; CHECK-LABEL: test2:
; CHECK: movsbl {{.*}}, %eax
}
define zeroext i16 @test3(i32 %y) nounwind {
%conv = trunc i32 %y to i16
ret i16 %conv
; CHECK-LABEL: test3:
; CHECK: movzwl {{.*}}, %eax
}
define signext i16 @test4(i32 %y) nounwind {
%conv = trunc i32 %y to i16
ret i16 %conv
; CHECK-LABEL: test4:
; CHECK: {{(movswl.%di, %eax|cwtl)}}
}
define zeroext i1 @test5(i32 %y) nounwind {
%conv = trunc i32 %y to i1
ret i1 %conv
; CHECK-LABEL: test5:
; CHECK: andb $1
; CHECK: movzbl {{.*}}, %eax
}