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llvm-mirror/test/CodeGen/X86/pr39098.ll
Guozhi Wei 36670f7ade [DAGCombine] Avoid CombineZExtLogicopShiftLoad if there is free ZEXT
This patch fixes pr39098.

For the attached test case, CombineZExtLogicopShiftLoad can optimize it to

t25: i64 = Constant<1099511627775>
t35: i64 = Constant<0>
  t0: ch = EntryToken
t57: i64,ch = load<(load 4 from `i40* undef`, align 8), zext from i32> t0, undef:i64, undef:i64
    t58: i64 = srl t57, Constant:i8<1>
  t60: i64 = and t58, Constant:i64<524287>
t29: ch = store<(store 5 into `i40* undef`, align 8), trunc to i40> t57:1, t60, undef:i64, undef:i64

But later visitANDLike transforms it to

t25: i64 = Constant<1099511627775>
t35: i64 = Constant<0>
  t0: ch = EntryToken
t57: i64,ch = load<(load 4 from `i40* undef`, align 8), zext from i32> t0, undef:i64, undef:i64
      t61: i32 = truncate t57
    t63: i32 = srl t61, Constant:i8<1>
  t64: i32 = and t63, Constant:i32<524287>
t65: i64 = zero_extend t64
    t58: i64 = srl t57, Constant:i8<1>
  t60: i64 = and t58, Constant:i64<524287>
t29: ch = store<(store 5 into `i40* undef`, align 8), trunc to i40> t57:1, t60, undef:i64, undef:i64

And it triggers CombineZExtLogicopShiftLoad again, causes a dead loop.

Both forms should generate same instructions, CombineZExtLogicopShiftLoad generated IR looks cleaner. But it looks more difficult to prevent visitANDLike to do the transform, so I prevent CombineZExtLogicopShiftLoad to do the transform if the ZExt is free.

Differential Revision: https://reviews.llvm.org/D57491

llvm-svn: 352792
2019-01-31 20:46:42 +00:00

21 lines
597 B
LLVM

; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
define dso_local void @test_cancel2(i40* %p1, i40* %p2) {
; CHECK: # %entry
; CHECK-NEXT: movl (%rdi), %eax
; CHECK-NEXT: shrl %eax
; CHECK-NEXT: andl $524287, %eax
; CHECK-NEXT: movl %eax, (%rsi)
; CHECK-NEXT: movb $0, 4(%rsi)
; CHECK-NEXT: retq
entry:
%0 = load i40, i40* %p1, align 8
%shl414 = shl i40 %0, 19
%unsclear415 = and i40 %shl414, 549755813887
%shr416 = lshr i40 %unsclear415, 20
%unsclear417 = and i40 %shr416, 549755813887
store i40 %unsclear417, i40* %p2, align 8
ret void
}