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4131403905
If extload is legal, following transform
(zext (select c, load1, load2)) -> (select c, zextload1, zextload2)
can save one ext instruction.
Differential Revision: https://reviews.llvm.org/D95086
147 lines
5.1 KiB
LLVM
147 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s
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; (zext(select c, load1, load2)) -> (select c, zextload1, zextload2)
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define i64 @zext_scalar(i8* %p, i1 zeroext %c) {
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; CHECK-LABEL: zext_scalar:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzbl (%rdi), %ecx
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; CHECK-NEXT: movzbl 1(%rdi), %eax
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; CHECK-NEXT: testl %esi, %esi
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; CHECK-NEXT: cmoveq %rcx, %rax
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; CHECK-NEXT: retq
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%ld1 = load volatile i8, i8* %p
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%arrayidx1 = getelementptr inbounds i8, i8* %p, i64 1
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%ld2 = load volatile i8, i8* %arrayidx1
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%cond.v = select i1 %c, i8 %ld2, i8 %ld1
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%cond = zext i8 %cond.v to i64
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ret i64 %cond
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}
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define i64 @zext_scalar2(i8* %p, i16* %q, i1 zeroext %c) {
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; CHECK-LABEL: zext_scalar2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzbl (%rdi), %ecx
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; CHECK-NEXT: movzwl (%rsi), %eax
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; CHECK-NEXT: testl %edx, %edx
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; CHECK-NEXT: cmoveq %rcx, %rax
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; CHECK-NEXT: retq
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%ld1 = load volatile i8, i8* %p
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%ext_ld1 = zext i8 %ld1 to i16
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%ld2 = load volatile i16, i16* %q
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%cond.v = select i1 %c, i16 %ld2, i16 %ext_ld1
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%cond = zext i16 %cond.v to i64
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ret i64 %cond
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}
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; Don't fold the ext if there is a load with conflicting ext type.
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define i64 @zext_scalar_neg(i8* %p, i16* %q, i1 zeroext %c) {
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; CHECK-LABEL: zext_scalar_neg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movsbl (%rdi), %eax
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; CHECK-NEXT: testl %edx, %edx
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; CHECK-NEXT: je .LBB2_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: movzwl (%rsi), %eax
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; CHECK-NEXT: .LBB2_2:
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; CHECK-NEXT: movzwl %ax, %eax
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; CHECK-NEXT: retq
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%ld1 = load volatile i8, i8* %p
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%ext_ld1 = sext i8 %ld1 to i16
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%ld2 = load volatile i16, i16* %q
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%cond.v = select i1 %c, i16 %ld2, i16 %ext_ld1
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%cond = zext i16 %cond.v to i64
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ret i64 %cond
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}
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; (sext(select c, load1, load2)) -> (select c, sextload1, sextload2)
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define i64 @sext_scalar(i8* %p, i1 zeroext %c) {
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; CHECK-LABEL: sext_scalar:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movsbq (%rdi), %rcx
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; CHECK-NEXT: movsbq 1(%rdi), %rax
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; CHECK-NEXT: testl %esi, %esi
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; CHECK-NEXT: cmoveq %rcx, %rax
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; CHECK-NEXT: retq
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%ld1 = load volatile i8, i8* %p
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%arrayidx1 = getelementptr inbounds i8, i8* %p, i64 1
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%ld2 = load volatile i8, i8* %arrayidx1
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%cond.v = select i1 %c, i8 %ld2, i8 %ld1
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%cond = sext i8 %cond.v to i64
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ret i64 %cond
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}
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; Same as zext_scalar, but operate on vectors.
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define <2 x i64> @zext_vector_i1(<2 x i32>* %p, i1 zeroext %c) {
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; CHECK-LABEL: zext_vector_i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pmovzxdq {{.*#+}} xmm1 = mem[0],zero,mem[1],zero
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; CHECK-NEXT: pmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
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; CHECK-NEXT: testl %esi, %esi
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; CHECK-NEXT: jne .LBB4_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: movdqa %xmm1, %xmm0
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; CHECK-NEXT: .LBB4_2:
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; CHECK-NEXT: retq
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%ld1 = load volatile <2 x i32>, <2 x i32>* %p
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%arrayidx1 = getelementptr inbounds <2 x i32>, <2 x i32>* %p, i64 1
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%ld2 = load volatile <2 x i32>, <2 x i32>* %arrayidx1
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%cond.v = select i1 %c, <2 x i32> %ld2, <2 x i32> %ld1
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%cond = zext <2 x i32> %cond.v to <2 x i64>
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ret <2 x i64> %cond
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}
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define <2 x i64> @zext_vector_v2i1(<2 x i32>* %p, <2 x i1> %c) {
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; CHECK-LABEL: zext_vector_v2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: psllq $63, %xmm0
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; CHECK-NEXT: pmovzxdq {{.*#+}} xmm1 = mem[0],zero,mem[1],zero
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; CHECK-NEXT: pmovzxdq {{.*#+}} xmm2 = mem[0],zero,mem[1],zero
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; CHECK-NEXT: blendvpd %xmm0, %xmm2, %xmm1
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; CHECK-NEXT: movapd %xmm1, %xmm0
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; CHECK-NEXT: retq
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%ld1 = load volatile <2 x i32>, <2 x i32>* %p
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%arrayidx1 = getelementptr inbounds <2 x i32>, <2 x i32>* %p, i64 1
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%ld2 = load volatile <2 x i32>, <2 x i32>* %arrayidx1
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%cond.v = select <2 x i1> %c, <2 x i32> %ld2, <2 x i32> %ld1
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%cond = zext <2 x i32> %cond.v to <2 x i64>
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ret <2 x i64> %cond
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}
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; Same as sext_scalar, but operate on vectors.
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define <2 x i64> @sext_vector_i1(<2 x i32>* %p, i1 zeroext %c) {
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; CHECK-LABEL: sext_vector_i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pmovsxdq (%rdi), %xmm1
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; CHECK-NEXT: pmovsxdq 8(%rdi), %xmm0
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; CHECK-NEXT: testl %esi, %esi
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; CHECK-NEXT: jne .LBB6_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: movdqa %xmm1, %xmm0
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; CHECK-NEXT: .LBB6_2:
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; CHECK-NEXT: retq
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%ld1 = load volatile <2 x i32>, <2 x i32>* %p
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%arrayidx1 = getelementptr inbounds <2 x i32>, <2 x i32>* %p, i64 1
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%ld2 = load volatile <2 x i32>, <2 x i32>* %arrayidx1
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%cond.v = select i1 %c, <2 x i32> %ld2, <2 x i32> %ld1
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%cond = sext <2 x i32> %cond.v to <2 x i64>
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ret <2 x i64> %cond
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}
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define <2 x i64> @sext_vector_v2i1(<2 x i32>* %p, <2 x i1> %c) {
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; CHECK-LABEL: sext_vector_v2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: psllq $63, %xmm0
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; CHECK-NEXT: pmovsxdq (%rdi), %xmm1
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; CHECK-NEXT: pmovsxdq 8(%rdi), %xmm2
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; CHECK-NEXT: blendvpd %xmm0, %xmm2, %xmm1
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; CHECK-NEXT: movapd %xmm1, %xmm0
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; CHECK-NEXT: retq
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%ld1 = load volatile <2 x i32>, <2 x i32>* %p
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%arrayidx1 = getelementptr inbounds <2 x i32>, <2 x i32>* %p, i64 1
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%ld2 = load volatile <2 x i32>, <2 x i32>* %arrayidx1
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%cond.v = select <2 x i1> %c, <2 x i32> %ld2, <2 x i32> %ld1
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%cond = sext <2 x i32> %cond.v to <2 x i64>
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ret <2 x i64> %cond
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}
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