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f8f9960480
We can just use a 32-bit copy and zero in the SSE domain when we zero the upper bits. Remove an isel pattern that becomes dead with this.
47 lines
1.3 KiB
LLVM
47 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
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; These should both generate something like this:
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;_test3:
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; movl $1234567, %eax
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; andl 4(%esp), %eax
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; movd %eax, %xmm0
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; ret
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define <2 x i64> @test3(i64 %arg) nounwind {
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; X86-LABEL: test3:
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; X86: # %bb.0:
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; X86-NEXT: movl $1234567, %eax # imm = 0x12D687
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; X86-NEXT: andl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movd %eax, %xmm0
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; X86-NEXT: retl
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;
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; X64-LABEL: test3:
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; X64: # %bb.0:
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; X64-NEXT: andl $1234567, %edi # imm = 0x12D687
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; X64-NEXT: movd %edi, %xmm0
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; X64-NEXT: retq
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%A = and i64 %arg, 1234567
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%B = insertelement <2 x i64> zeroinitializer, i64 %A, i32 0
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ret <2 x i64> %B
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}
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define <2 x i64> @test2(i64 %arg) nounwind {
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; X86-LABEL: test2:
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; X86: # %bb.0:
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; X86-NEXT: movl $1234567, %eax # imm = 0x12D687
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; X86-NEXT: andl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movd %eax, %xmm0
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; X86-NEXT: retl
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;
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; X64-LABEL: test2:
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; X64: # %bb.0:
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; X64-NEXT: andl $1234567, %edi # imm = 0x12D687
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; X64-NEXT: movq %rdi, %xmm0
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; X64-NEXT: retq
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%A = and i64 %arg, 1234567
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%B = insertelement <2 x i64> undef, i64 %A, i32 0
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ret <2 x i64> %B
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}
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