mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-02-01 13:11:39 +01:00
262321d1ff
This patch lets the llvm tools handle the new HVX target features that
are added by frontend (clang). The target-features are of the form
"hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX.
"hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated.
The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}.
Eg: "+hvxv62"
For the correct HVX code generation, the user must use the following
target features.
For 64B mode: "+hvxv62" "+hvx-length64b"
For 128B mode: "+hvxv62" "+hvx-length128b"
Clang picks a default length if none is specified. If for some reason,
no hvx-length is specified to llvm, the compilation will bail out.
There is a corresponding clang patch.
Differential Revision: https://reviews.llvm.org/D38851
llvm-svn: 316101
34 lines
1.3 KiB
LLVM
34 lines
1.3 KiB
LLVM
; RUN: llc -march=hexagon -mattr="+hvxv60,+hvx-length64b" < %s
|
|
; REQUIRES: asserts
|
|
|
|
target triple = "hexagon"
|
|
|
|
; Function Attrs: nounwind
|
|
define void @fred() #0 {
|
|
entry:
|
|
br label %for.body9.us
|
|
|
|
for.body9.us:
|
|
%cmp10.us = icmp eq i32 0, undef
|
|
%.h63h32.2.us = select i1 %cmp10.us, <16 x i32> zeroinitializer, <16 x i32> undef
|
|
%0 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %.h63h32.2.us, <16 x i32> undef, i32 2)
|
|
%1 = tail call <32 x i32> @llvm.hexagon.V6.vswap(<512 x i1> undef, <16 x i32> undef, <16 x i32> %0)
|
|
%2 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %1)
|
|
%3 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> undef, <16 x i32> %2, i32 62)
|
|
%4 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %3)
|
|
store <16 x i32> %4, <16 x i32>* undef, align 64
|
|
br i1 undef, label %for.body9.us, label %for.body43.us.preheader
|
|
|
|
for.body43.us.preheader: ; preds = %for.body9.us
|
|
ret void
|
|
}
|
|
|
|
declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1
|
|
declare <32 x i32> @llvm.hexagon.V6.vswap(<512 x i1>, <16 x i32>, <16 x i32>) #1
|
|
declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
|
|
declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
|
|
declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #1
|
|
|
|
attributes #0 = { nounwind }
|
|
attributes #1 = { nounwind readnone }
|