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b1775ae908
If we are and the constant like 0xFFFFFFC00000, for now, we are using several
instructions to generate this 48bit constant and final an "and". However, we
could exploit it with two rotate instructions.
MB ME MB+63-ME
+----------------------+ +----------------------+
|0000001111111111111000| -> |0000000001111111111111|
+----------------------+ +----------------------+
0 63 0 63
Rotate left ME + 1 bit first, and then, mask it with (MB + 63 - ME, 63),
finally, rotate back. Notice that, we need to round it with 64 bit for the
wrapping case.
Reviewed by: ChenZheng, Nemanjai
Differential Revision: https://reviews.llvm.org/D71831
27 lines
903 B
LLVM
27 lines
903 B
LLVM
; RUN: llc -verify-machineinstrs <%s | FileCheck %s
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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; PR27390 crasher
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%typ = type { i32, i32 }
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; On release builds, it doesn't crash, spewing nonsense instead.
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; To make sure it works, check that rldicl is still alive.
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; CHECK: rldicl
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; Also, in release, it emits a COPY from a 32-bit register to
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; a 64-bit register, which happens to be emitted as cror [!]
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; by the confused CodeGen. Just to be sure, check there isn't one.
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; CHECK-NOT: cror
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; Function Attrs: uwtable
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define signext i32 @_Z8access_pP1Tc(%typ* %p, i8 zeroext %type) {
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%b = getelementptr inbounds %typ, %typ* %p, i64 0, i32 1
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%1 = load i32, i32* %b, align 4
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%2 = ptrtoint i32* %b to i64
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%3 = and i64 %2, -35184372088833
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%4 = inttoptr i64 %3 to i32*
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%_msld = load i32, i32* %4, align 4
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%zzz = add i32 %1, %_msld
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ret i32 %zzz
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}
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