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Mirror of https://github.com/RPCS3/llvm-mirror
60bfb5d707
our current machine instruction defines a register with the same register class as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it would ICE because a tail call was expecting one register class but was given another. (The machine instruction verifier catches this situation.) <rdar://problem/10270968> llvm-svn: 141830 |
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autoconf | ||
bindings | ||
cmake | ||
docs | ||
examples | ||
include | ||
lib | ||
projects | ||
runtime | ||
test | ||
tools | ||
unittests | ||
utils | ||
.gitignore | ||
build-for-llvm-top.sh | ||
CMakeLists.txt | ||
configure | ||
CREDITS.TXT | ||
LICENSE.TXT | ||
llvm.spec.in | ||
Makefile | ||
Makefile.common | ||
Makefile.config.in | ||
Makefile.rules | ||
ModuleInfo.txt | ||
README.txt |
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