mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 19:23:23 +01:00
60bfb5d707
our current machine instruction defines a register with the same register class as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it would ICE because a tail call was expecting one register class but was given another. (The machine instruction verifier catches this situation.) <rdar://problem/10270968> llvm-svn: 141830 |
||
---|---|---|
.. | ||
Analysis | ||
Archive | ||
Assembler | ||
Bindings/Ocaml | ||
Bitcode | ||
BugPoint | ||
CodeGen | ||
DebugInfo | ||
ExecutionEngine | ||
Feature | ||
Integer | ||
lib | ||
Linker | ||
MC | ||
Object | ||
Other | ||
Scripts | ||
TableGen | ||
Transforms | ||
Unit | ||
Verifier | ||
CMakeLists.txt | ||
lit.cfg | ||
lit.site.cfg.in | ||
Makefile | ||
Makefile.tests | ||
site.exp.in | ||
TestRunner.sh |