mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-20 19:42:54 +02:00
4cf61e5269
Summary: The bug was that dextu's operand 3 would print 0-31 instead of 32-63 when printing assembly. This came up when replacing MipsInstPrinter::printUnsignedImm() with a version that could handle arbitrary bit widths. MipsAsmPrinter::printUnsignedImm*() don't seem to be used so they have been removed. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15521 llvm-svn: 262231
58 lines
1.4 KiB
LLVM
58 lines
1.4 KiB
LLVM
; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -target-abi=n64 %s -o - \
|
|
; RUN: | llvm-objdump -disassemble -triple mips64el -mattr +mips64r2 - \
|
|
; RUN: | FileCheck %s
|
|
|
|
define i64 @dext(i64 %i) nounwind readnone {
|
|
entry:
|
|
; CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10
|
|
%shr = lshr i64 %i, 5
|
|
%and = and i64 %shr, 1023
|
|
ret i64 %and
|
|
}
|
|
|
|
define i64 @dextu(i64 %i) nounwind readnone {
|
|
entry:
|
|
; CHECK: dextu ${{[0-9]+}}, ${{[0-9]+}}, 34, 6
|
|
%shr = lshr i64 %i, 34
|
|
%and = and i64 %shr, 63
|
|
ret i64 %and
|
|
}
|
|
|
|
define i64 @dextm(i64 %i) nounwind readnone {
|
|
entry:
|
|
; CHECK: dextm ${{[0-9]+}}, ${{[0-9]+}}, 5, 34
|
|
%shr = lshr i64 %i, 5
|
|
%and = and i64 %shr, 17179869183
|
|
ret i64 %and
|
|
}
|
|
|
|
define i64 @dins(i64 %i, i64 %j) nounwind readnone {
|
|
entry:
|
|
; CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 8, 10
|
|
%shl2 = shl i64 %j, 8
|
|
%and = and i64 %shl2, 261888
|
|
%and3 = and i64 %i, -261889
|
|
%or = or i64 %and3, %and
|
|
ret i64 %or
|
|
}
|
|
|
|
define i64 @dinsm(i64 %i, i64 %j) nounwind readnone {
|
|
entry:
|
|
; CHECK: dinsm ${{[0-9]+}}, ${{[0-9]+}}, 10, 1
|
|
%shl4 = shl i64 %j, 10
|
|
%and = and i64 %shl4, 8796093021184
|
|
%and5 = and i64 %i, -8796093021185
|
|
%or = or i64 %and5, %and
|
|
ret i64 %or
|
|
}
|
|
|
|
define i64 @dinsu(i64 %i, i64 %j) nounwind readnone {
|
|
entry:
|
|
; CHECK: dinsu ${{[0-9]+}}, ${{[0-9]+}}, 40, 13
|
|
%shl4 = shl i64 %j, 40
|
|
%and = and i64 %shl4, 9006099743113216
|
|
%and5 = and i64 %i, -9006099743113217
|
|
%or = or i64 %and5, %and
|
|
ret i64 %or
|
|
}
|