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e7725047a0
I've included a fix to DAGCombiner::ForwardStoreValueToDirectLoad that I believe will prevent the previous miscompile. Original commit message: Theoretically this was done to simplify the amount of isel patterns that were needed. But it also meant a substantial number of our isel patterns have to match an explicit bitcast. By making the vXi32/vXi16/vXi8 types legal for loads, DAG combiner should be able to change the load type to rem I had to add some additional plain load instruction patterns and a few other special cases, but overall the isel table has reduced in size by ~12000 bytes. So it looks like this promotion was hurting us more than helping. I still have one crash in vector-trunc.ll that I'm hoping @RKSimon can help with. It seems to relate to using getTargetConstantFromNode on a load that was shrunk due to an extract_subvector combine after the constant pool entry was created. So we end up decoding more mask elements than the lo I'm hoping this patch will simplify the number of patterns needed to remove the and/or/xor promotion. Reviewers: RKSimon, spatel Reviewed By: RKSimon Subscribers: llvm-commits, RKSimon Differential Revision: https://reviews.llvm.org/D53306 llvm-svn: 344965
348 lines
11 KiB
C++
348 lines
11 KiB
C++
//===-- X86ShuffleDecodeConstantPool.cpp - X86 shuffle decode -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Define several functions to decode x86 specific shuffle semantics using
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// constants from the constant pool.
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//
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//===----------------------------------------------------------------------===//
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#include "Utils/X86ShuffleDecode.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/IR/Constants.h"
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//===----------------------------------------------------------------------===//
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// Vector Mask Decoding
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//===----------------------------------------------------------------------===//
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namespace llvm {
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static bool extractConstantMask(const Constant *C, unsigned MaskEltSizeInBits,
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APInt &UndefElts,
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SmallVectorImpl<uint64_t> &RawMask) {
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// It is not an error for shuffle masks to not be a vector of
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// MaskEltSizeInBits because the constant pool uniques constants by their
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// bit representation.
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// e.g. the following take up the same space in the constant pool:
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// i128 -170141183420855150465331762880109871104
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//
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// <2 x i64> <i64 -9223372034707292160, i64 -9223372034707292160>
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//
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// <4 x i32> <i32 -2147483648, i32 -2147483648,
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// i32 -2147483648, i32 -2147483648>
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Type *CstTy = C->getType();
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if (!CstTy->isVectorTy())
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return false;
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Type *CstEltTy = CstTy->getVectorElementType();
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if (!CstEltTy->isIntegerTy())
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return false;
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unsigned CstSizeInBits = CstTy->getPrimitiveSizeInBits();
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unsigned CstEltSizeInBits = CstTy->getScalarSizeInBits();
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unsigned NumCstElts = CstTy->getVectorNumElements();
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assert((CstSizeInBits % MaskEltSizeInBits) == 0 &&
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"Unaligned shuffle mask size");
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unsigned NumMaskElts = CstSizeInBits / MaskEltSizeInBits;
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UndefElts = APInt(NumMaskElts, 0);
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RawMask.resize(NumMaskElts, 0);
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// Fast path - if the constants match the mask size then copy direct.
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if (MaskEltSizeInBits == CstEltSizeInBits) {
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assert(NumCstElts == NumMaskElts && "Unaligned shuffle mask size");
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for (unsigned i = 0; i != NumMaskElts; ++i) {
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Constant *COp = C->getAggregateElement(i);
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if (!COp || (!isa<UndefValue>(COp) && !isa<ConstantInt>(COp)))
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return false;
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if (isa<UndefValue>(COp)) {
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UndefElts.setBit(i);
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RawMask[i] = 0;
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continue;
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}
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auto *Elt = cast<ConstantInt>(COp);
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RawMask[i] = Elt->getValue().getZExtValue();
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}
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return true;
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}
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// Extract all the undef/constant element data and pack into single bitsets.
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APInt UndefBits(CstSizeInBits, 0);
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APInt MaskBits(CstSizeInBits, 0);
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for (unsigned i = 0; i != NumCstElts; ++i) {
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Constant *COp = C->getAggregateElement(i);
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if (!COp || (!isa<UndefValue>(COp) && !isa<ConstantInt>(COp)))
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return false;
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unsigned BitOffset = i * CstEltSizeInBits;
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if (isa<UndefValue>(COp)) {
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UndefBits.setBits(BitOffset, BitOffset + CstEltSizeInBits);
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continue;
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}
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MaskBits.insertBits(cast<ConstantInt>(COp)->getValue(), BitOffset);
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}
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// Now extract the undef/constant bit data into the raw shuffle masks.
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for (unsigned i = 0; i != NumMaskElts; ++i) {
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unsigned BitOffset = i * MaskEltSizeInBits;
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APInt EltUndef = UndefBits.extractBits(MaskEltSizeInBits, BitOffset);
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// Only treat the element as UNDEF if all bits are UNDEF, otherwise
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// treat it as zero.
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if (EltUndef.isAllOnesValue()) {
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UndefElts.setBit(i);
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RawMask[i] = 0;
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continue;
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}
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APInt EltBits = MaskBits.extractBits(MaskEltSizeInBits, BitOffset);
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RawMask[i] = EltBits.getZExtValue();
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}
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return true;
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}
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void DecodePSHUFBMask(const Constant *C, unsigned Width,
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SmallVectorImpl<int> &ShuffleMask) {
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assert((Width == 128 || Width == 256 || Width == 512) &&
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C->getType()->getPrimitiveSizeInBits() >= Width &&
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"Unexpected vector size.");
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// The shuffle mask requires a byte vector.
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APInt UndefElts;
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SmallVector<uint64_t, 64> RawMask;
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if (!extractConstantMask(C, 8, UndefElts, RawMask))
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return;
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unsigned NumElts = Width / 8;
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assert((NumElts == 16 || NumElts == 32 || NumElts == 64) &&
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"Unexpected number of vector elements.");
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for (unsigned i = 0; i != NumElts; ++i) {
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if (UndefElts[i]) {
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ShuffleMask.push_back(SM_SentinelUndef);
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continue;
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}
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uint64_t Element = RawMask[i];
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// If the high bit (7) of the byte is set, the element is zeroed.
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if (Element & (1 << 7))
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ShuffleMask.push_back(SM_SentinelZero);
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else {
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// For AVX vectors with 32 bytes the base of the shuffle is the 16-byte
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// lane of the vector we're inside.
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unsigned Base = i & ~0xf;
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// Only the least significant 4 bits of the byte are used.
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int Index = Base + (Element & 0xf);
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ShuffleMask.push_back(Index);
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}
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}
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}
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void DecodeVPERMILPMask(const Constant *C, unsigned ElSize, unsigned Width,
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SmallVectorImpl<int> &ShuffleMask) {
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assert((Width == 128 || Width == 256 || Width == 512) &&
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C->getType()->getPrimitiveSizeInBits() >= Width &&
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"Unexpected vector size.");
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assert((ElSize == 32 || ElSize == 64) && "Unexpected vector element size.");
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// The shuffle mask requires elements the same size as the target.
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APInt UndefElts;
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SmallVector<uint64_t, 16> RawMask;
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if (!extractConstantMask(C, ElSize, UndefElts, RawMask))
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return;
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unsigned NumElts = Width / ElSize;
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unsigned NumEltsPerLane = 128 / ElSize;
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assert((NumElts == 2 || NumElts == 4 || NumElts == 8 || NumElts == 16) &&
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"Unexpected number of vector elements.");
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for (unsigned i = 0; i != NumElts; ++i) {
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if (UndefElts[i]) {
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ShuffleMask.push_back(SM_SentinelUndef);
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continue;
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}
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int Index = i & ~(NumEltsPerLane - 1);
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uint64_t Element = RawMask[i];
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if (ElSize == 64)
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Index += (Element >> 1) & 0x1;
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else
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Index += Element & 0x3;
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ShuffleMask.push_back(Index);
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}
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}
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void DecodeVPERMIL2PMask(const Constant *C, unsigned M2Z, unsigned ElSize,
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unsigned Width,
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SmallVectorImpl<int> &ShuffleMask) {
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Type *MaskTy = C->getType();
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unsigned MaskTySize = MaskTy->getPrimitiveSizeInBits();
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(void)MaskTySize;
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assert((MaskTySize == 128 || MaskTySize == 256) &&
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Width >= MaskTySize && "Unexpected vector size.");
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// The shuffle mask requires elements the same size as the target.
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APInt UndefElts;
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SmallVector<uint64_t, 8> RawMask;
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if (!extractConstantMask(C, ElSize, UndefElts, RawMask))
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return;
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unsigned NumElts = Width / ElSize;
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unsigned NumEltsPerLane = 128 / ElSize;
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assert((NumElts == 2 || NumElts == 4 || NumElts == 8) &&
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"Unexpected number of vector elements.");
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for (unsigned i = 0; i != NumElts; ++i) {
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if (UndefElts[i]) {
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ShuffleMask.push_back(SM_SentinelUndef);
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continue;
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}
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// VPERMIL2 Operation.
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// Bits[3] - Match Bit.
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// Bits[2:1] - (Per Lane) PD Shuffle Mask.
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// Bits[2:0] - (Per Lane) PS Shuffle Mask.
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uint64_t Selector = RawMask[i];
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unsigned MatchBit = (Selector >> 3) & 0x1;
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// M2Z[0:1] MatchBit
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// 0Xb X Source selected by Selector index.
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// 10b 0 Source selected by Selector index.
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// 10b 1 Zero.
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// 11b 0 Zero.
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// 11b 1 Source selected by Selector index.
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if ((M2Z & 0x2) != 0u && MatchBit != (M2Z & 0x1)) {
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ShuffleMask.push_back(SM_SentinelZero);
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continue;
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}
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int Index = i & ~(NumEltsPerLane - 1);
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if (ElSize == 64)
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Index += (Selector >> 1) & 0x1;
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else
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Index += Selector & 0x3;
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int Src = (Selector >> 2) & 0x1;
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Index += Src * NumElts;
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ShuffleMask.push_back(Index);
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}
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}
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void DecodeVPPERMMask(const Constant *C, unsigned Width,
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SmallVectorImpl<int> &ShuffleMask) {
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Type *MaskTy = C->getType();
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unsigned MaskTySize = MaskTy->getPrimitiveSizeInBits();
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(void)MaskTySize;
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assert(Width == 128 && Width >= MaskTySize && "Unexpected vector size.");
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// The shuffle mask requires a byte vector.
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APInt UndefElts;
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SmallVector<uint64_t, 16> RawMask;
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if (!extractConstantMask(C, 8, UndefElts, RawMask))
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return;
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unsigned NumElts = Width / 8;
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assert(NumElts == 16 && "Unexpected number of vector elements.");
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for (unsigned i = 0; i != NumElts; ++i) {
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if (UndefElts[i]) {
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ShuffleMask.push_back(SM_SentinelUndef);
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continue;
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}
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// VPPERM Operation
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// Bits[4:0] - Byte Index (0 - 31)
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// Bits[7:5] - Permute Operation
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//
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// Permute Operation:
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// 0 - Source byte (no logical operation).
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// 1 - Invert source byte.
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// 2 - Bit reverse of source byte.
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// 3 - Bit reverse of inverted source byte.
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// 4 - 00h (zero - fill).
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// 5 - FFh (ones - fill).
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// 6 - Most significant bit of source byte replicated in all bit positions.
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// 7 - Invert most significant bit of source byte and replicate in all bit
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// positions.
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uint64_t Element = RawMask[i];
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uint64_t Index = Element & 0x1F;
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uint64_t PermuteOp = (Element >> 5) & 0x7;
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if (PermuteOp == 4) {
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ShuffleMask.push_back(SM_SentinelZero);
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continue;
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}
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if (PermuteOp != 0) {
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ShuffleMask.clear();
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return;
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}
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ShuffleMask.push_back((int)Index);
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}
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}
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void DecodeVPERMVMask(const Constant *C, unsigned ElSize, unsigned Width,
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SmallVectorImpl<int> &ShuffleMask) {
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assert((Width == 128 || Width == 256 || Width == 512) &&
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C->getType()->getPrimitiveSizeInBits() >= Width &&
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"Unexpected vector size.");
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assert((ElSize == 8 || ElSize == 16 || ElSize == 32 || ElSize == 64) &&
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"Unexpected vector element size.");
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// The shuffle mask requires elements the same size as the target.
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APInt UndefElts;
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SmallVector<uint64_t, 64> RawMask;
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if (!extractConstantMask(C, ElSize, UndefElts, RawMask))
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return;
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unsigned NumElts = Width / ElSize;
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for (unsigned i = 0; i != NumElts; ++i) {
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if (UndefElts[i]) {
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ShuffleMask.push_back(SM_SentinelUndef);
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continue;
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}
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int Index = RawMask[i] & (NumElts - 1);
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ShuffleMask.push_back(Index);
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}
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}
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void DecodeVPERMV3Mask(const Constant *C, unsigned ElSize, unsigned Width,
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SmallVectorImpl<int> &ShuffleMask) {
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assert((Width == 128 || Width == 256 || Width == 512) &&
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C->getType()->getPrimitiveSizeInBits() >= Width &&
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"Unexpected vector size.");
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assert((ElSize == 8 || ElSize == 16 || ElSize == 32 || ElSize == 64) &&
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"Unexpected vector element size.");
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// The shuffle mask requires elements the same size as the target.
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APInt UndefElts;
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SmallVector<uint64_t, 64> RawMask;
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if (!extractConstantMask(C, ElSize, UndefElts, RawMask))
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return;
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unsigned NumElts = Width / ElSize;
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for (unsigned i = 0; i != NumElts; ++i) {
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if (UndefElts[i]) {
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ShuffleMask.push_back(SM_SentinelUndef);
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continue;
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}
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int Index = RawMask[i] & (NumElts*2 - 1);
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ShuffleMask.push_back(Index);
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}
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}
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} // llvm namespace
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