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60e97a1d60
Missing these could potentially screw up post-ra scheduling. Issue found by inspection, so I don't have a real testcase. Included test just verifies the expected operands after expansion. Differential Revision: https://reviews.llvm.org/D35156 llvm-svn: 312589
76 lines
1.7 KiB
YAML
76 lines
1.7 KiB
YAML
# RUN: llc -run-pass=arm-pseudo -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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target triple = "armv7---gnueabi"
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define i32 @test1(i32 %x) {
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entry:
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unreachable
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}
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define i32 @test2(i32 %x) {
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entry:
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unreachable
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}
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define i32 @test3(i32 %x) {
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entry:
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unreachable
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}
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...
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---
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name: test1
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alignment: 2
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tracksRegLiveness: true
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liveins:
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- { reg: '%r0', virtual-reg: '' }
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body: |
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bb.0.entry:
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liveins: %r0
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%r1 = MOVi 2, 14, _, _
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CMPri killed %r0, 0, 14, _, implicit-def %cpsr
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%r1 = MOVCCi16 killed %r1, 500, 0, killed %cpsr
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%r0 = MOVr killed %r1, 14, _, _
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BX_RET 14, _, implicit %r0
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...
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---
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name: test2
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alignment: 2
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tracksRegLiveness: true
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liveins:
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- { reg: '%r0', virtual-reg: '' }
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body: |
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bb.0.entry:
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liveins: %r0
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%r1 = MOVi 2, 14, _, _
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CMPri killed %r0, 0, 14, _, implicit-def %cpsr
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%r1 = MOVCCi32imm killed %r1, 500500500, 0, killed %cpsr
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%r0 = MOVr killed %r1, 14, _, _
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BX_RET 14, _, implicit %r0
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...
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---
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name: test3
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alignment: 2
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tracksRegLiveness: true
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liveins:
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- { reg: '%r0', virtual-reg: '' }
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- { reg: '%r1', virtual-reg: '' }
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body: |
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bb.0.entry:
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liveins: %r0, %r1
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CMPri %r1, 500, 14, _, implicit-def %cpsr
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%r0 = MOVCCr killed %r0, killed %r1, 12, killed %cpsr
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BX_RET 14, _, implicit %r0
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...
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# CHECK-LABEL: name: test1
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# CHECK: %r1 = MOVi16 500, 0, killed %cpsr, implicit killed %r1
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# CHECK-LABEL: name: test2
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# CHECK: %r1 = MOVi16 2068, 0, %cpsr, implicit killed %r1
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# CHECK: %r1 = MOVTi16 %r1, 7637, 0, %cpsr
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# CHECK-LABEL: name: test3
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# CHECK: %r0 = MOVr killed %r1, 12, killed %cpsr, _, implicit killed %r0
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