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a96193f77c
Re-commit of r258951 after fixing layering violation. The BPF and WebAssembly backends had identical code for emitting errors for unsupported features, and AMDGPU had very similar code. This merges them all into one DiagnosticInfo subclass, that can be used by any backend. There should be minimal functional changes here, but some AMDGPU tests have been updated for the new format of errors (it used a slightly different format to BPF and WebAssembly). The AMDGPU error messages will now benefit from having precise source locations when debug info is available. llvm-svn: 259498
67 lines
2.6 KiB
LLVM
67 lines
2.6 KiB
LLVM
; RUN: not llc -O0 -march=amdgcn -mcpu=bonaire -mattr=-promote-alloca < %s 2>&1 | FileCheck -check-prefix=ERROR %s
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; ERROR: addrspacecast not implemented
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; XUN: llc -O0 -march=amdgcn -mcpu=bonaire -mattr=-promote-alloca < %s | FileCheck -check-prefix=CHECK -check-prefix=CHECK-NO-PROMOTE %s
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; XUN: llc -O0 -march=amdgcn -mcpu=bonaire -mattr=+promote-alloca < %s | FileCheck -check-prefix=CHECK -check-prefix=CHECK-PROMOTE %s
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; XUN: llc -O0 -march=amdgcn -mcpu=tonga -mattr=-promote-alloca < %s | FileCheck -check-prefix=CHECK -check-prefix=CHECK-NO-PROMOTE %s
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; XUN: llc -O0 -march=amdgcn -mcpu=tonga -mattr=+promote-alloca < %s | FileCheck -check-prefix=CHECK -check-prefix=CHECK-PROMOTE %s
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; Disable optimizations in case there are optimizations added that
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; specialize away generic pointer accesses.
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; CHECK-LABEL: {{^}}branch_use_flat_i32:
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; CHECK: flat_store_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}
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; CHECK: s_endpgm
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define void @branch_use_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* %gptr, i32 addrspace(3)* %lptr, i32 %x, i32 %c) #0 {
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entry:
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%cmp = icmp ne i32 %c, 0
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br i1 %cmp, label %local, label %global
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local:
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%flat_local = addrspacecast i32 addrspace(3)* %lptr to i32 addrspace(4)*
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br label %end
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global:
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%flat_global = addrspacecast i32 addrspace(1)* %gptr to i32 addrspace(4)*
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br label %end
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end:
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%fptr = phi i32 addrspace(4)* [ %flat_local, %local ], [ %flat_global, %global ]
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store i32 %x, i32 addrspace(4)* %fptr, align 4
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; %val = load i32, i32 addrspace(4)* %fptr, align 4
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; store i32 %val, i32 addrspace(1)* %out, align 4
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ret void
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}
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; TODO: This should not be zero when registers are used for small
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; scratch allocations again.
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; Check for prologue initializing special SGPRs pointing to scratch.
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; CHECK-LABEL: {{^}}store_flat_scratch:
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; CHECK: s_movk_i32 flat_scratch_lo, 0
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; CHECK-NO-PROMOTE: s_movk_i32 flat_scratch_hi, 0x28{{$}}
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; CHECK-PROMOTE: s_movk_i32 flat_scratch_hi, 0x0{{$}}
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; CHECK: flat_store_dword
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; CHECK: s_barrier
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; CHECK: flat_load_dword
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define void @store_flat_scratch(i32 addrspace(1)* noalias %out, i32) #0 {
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%alloca = alloca i32, i32 9, align 4
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%x = call i32 @llvm.r600.read.tidig.x() #3
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%pptr = getelementptr i32, i32* %alloca, i32 %x
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%fptr = addrspacecast i32* %pptr to i32 addrspace(4)*
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store i32 %x, i32 addrspace(4)* %fptr
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; Dummy call
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call void @llvm.AMDGPU.barrier.local() #1
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%reload = load i32, i32 addrspace(4)* %fptr, align 4
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store i32 %reload, i32 addrspace(1)* %out, align 4
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ret void
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}
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declare void @llvm.AMDGPU.barrier.local() #1
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declare i32 @llvm.r600.read.tidig.x() #3
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attributes #0 = { nounwind }
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attributes #1 = { nounwind convergent }
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attributes #3 = { nounwind readnone }
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