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28c28a361a
This stops using an unknown reg class operand. Currently build_vector selection has a broken looking check where it tries to use a VGPR reg class and an SGPR one if it sees an SGPR use. With the source operand has an explicit VGPR class, illegal copies will be inserted that SIFixSGPRCopies will take care of normally later, which will allow removing the weird check of build_vector users. Without this, when removed v_movrels_b32 would still be emitted even though all of the values were only stored in SGPRs. llvm-svn: 249494
179 lines
6.6 KiB
LLVM
179 lines
6.6 KiB
LLVM
; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
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; Tests for indirect addressing on SI, which is implemented using dynamic
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; indexing of vectors.
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; CHECK-LABEL: {{^}}extract_w_offset:
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; CHECK-DAG: v_mov_b32_e32 v{{[0-9]+}}, 4.0
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; CHECK-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x40400000
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; CHECK-DAG: v_mov_b32_e32 v{{[0-9]+}}, 2.0
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; CHECK-DAG: v_mov_b32_e32 v{{[0-9]+}}, 1.0
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; CHECK: s_mov_b32 m0
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; CHECK-NEXT: v_movrels_b32_e32
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define void @extract_w_offset(float addrspace(1)* %out, i32 %in) {
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entry:
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%idx = add i32 %in, 1
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%elt = extractelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, i32 %idx
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store float %elt, float addrspace(1)* %out
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ret void
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}
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; XXX: Could do v_or_b32 directly
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; CHECK-LABEL: {{^}}extract_w_offset_salu_use_vector:
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; CHECK-DAG: s_or_b32
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; CHECK-DAG: s_or_b32
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; CHECK-DAG: s_or_b32
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; CHECK-DAG: s_or_b32
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; CHECK-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
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; CHECK-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
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; CHECK-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
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; CHECK-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
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; CHECK: s_mov_b32 m0
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; CHECK-NEXT: v_movrels_b32_e32
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define void @extract_w_offset_salu_use_vector(i32 addrspace(1)* %out, i32 %in, <4 x i32> %or.val) {
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entry:
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%idx = add i32 %in, 1
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%vec = or <4 x i32> %or.val, <i32 1, i32 2, i32 3, i32 4>
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%elt = extractelement <4 x i32> %vec, i32 %idx
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store i32 %elt, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}extract_wo_offset:
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; CHECK-DAG: v_mov_b32_e32 v{{[0-9]+}}, 4.0
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; CHECK-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0x40400000
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; CHECK-DAG: v_mov_b32_e32 v{{[0-9]+}}, 2.0
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; CHECK-DAG: v_mov_b32_e32 v{{[0-9]+}}, 1.0
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; CHECK: s_mov_b32 m0
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; CHECK-NEXT: v_movrels_b32_e32
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define void @extract_wo_offset(float addrspace(1)* %out, i32 %in) {
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entry:
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%elt = extractelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, i32 %in
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store float %elt, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}extract_neg_offset_sgpr:
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; The offset depends on the register that holds the first element of the vector.
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; CHECK: s_add_i32 m0, s{{[0-9]+}}, 0xfffffe{{[0-9a-z]+}}
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; CHECK: v_movrels_b32_e32 v{{[0-9]}}, v0
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define void @extract_neg_offset_sgpr(i32 addrspace(1)* %out, i32 %offset) {
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entry:
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%index = add i32 %offset, -512
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%value = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %index
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store i32 %value, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}extract_neg_offset_sgpr_loaded:
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; The offset depends on the register that holds the first element of the vector.
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; CHECK: s_add_i32 m0, s{{[0-9]+}}, 0xfffffe{{[0-9a-z]+}}
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; CHECK: v_movrels_b32_e32 v{{[0-9]}}, v0
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define void @extract_neg_offset_sgpr_loaded(i32 addrspace(1)* %out, <4 x i32> %vec0, <4 x i32> %vec1, i32 %offset) {
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entry:
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%index = add i32 %offset, -512
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%or = or <4 x i32> %vec0, %vec1
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%value = extractelement <4 x i32> %or, i32 %index
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store i32 %value, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}extract_neg_offset_vgpr:
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; The offset depends on the register that holds the first element of the vector.
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; CHECK: v_readfirstlane_b32
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; CHECK: s_add_i32 m0, m0, 0xfffffe{{[0-9a-z]+}}
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; CHECK-NEXT: v_movrels_b32_e32 v{{[0-9]}}, v0
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; CHECK: s_cbranch_execnz
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define void @extract_neg_offset_vgpr(i32 addrspace(1)* %out) {
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entry:
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%id = call i32 @llvm.r600.read.tidig.x() #1
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%index = add i32 %id, -512
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%value = extractelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %index
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store i32 %value, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}insert_w_offset:
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; CHECK: s_mov_b32 m0
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; CHECK-NEXT: v_movreld_b32_e32
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define void @insert_w_offset(float addrspace(1)* %out, i32 %in) {
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entry:
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%0 = add i32 %in, 1
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%1 = insertelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, float 5.0, i32 %0
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%2 = extractelement <4 x float> %1, i32 2
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store float %2, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}insert_wo_offset:
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; CHECK: s_mov_b32 m0
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; CHECK-NEXT: v_movreld_b32_e32
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define void @insert_wo_offset(float addrspace(1)* %out, i32 %in) {
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entry:
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%0 = insertelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, float 5.0, i32 %in
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%1 = extractelement <4 x float> %0, i32 2
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store float %1, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}insert_neg_offset_sgpr:
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; The offset depends on the register that holds the first element of the vector.
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; CHECK: s_add_i32 m0, s{{[0-9]+}}, 0xfffffe{{[0-9a-z]+}}
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; CHECK: v_movreld_b32_e32 v0, v{{[0-9]}}
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define void @insert_neg_offset_sgpr(i32 addrspace(1)* %in, <4 x i32> addrspace(1)* %out, i32 %offset) {
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entry:
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%index = add i32 %offset, -512
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%value = insertelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 5, i32 %index
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store <4 x i32> %value, <4 x i32> addrspace(1)* %out
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ret void
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}
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; The vector indexed into is originally loaded into an SGPR rather
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; than built with a reg_sequence
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; CHECK-LABEL: {{^}}insert_neg_offset_sgpr_loadreg:
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; The offset depends on the register that holds the first element of the vector.
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; CHECK: s_add_i32 m0, s{{[0-9]+}}, 0xfffffe{{[0-9a-z]+}}
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; CHECK: v_movreld_b32_e32 v0, v{{[0-9]}}
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define void @insert_neg_offset_sgpr_loadreg(i32 addrspace(1)* %in, <4 x i32> addrspace(1)* %out, <4 x i32> %vec, i32 %offset) {
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entry:
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%index = add i32 %offset, -512
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%value = insertelement <4 x i32> %vec, i32 5, i32 %index
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store <4 x i32> %value, <4 x i32> addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}insert_neg_offset_vgpr:
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; The offset depends on the register that holds the first element of the vector.
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; CHECK: v_readfirstlane_b32
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; CHECK: s_add_i32 m0, m0, 0xfffffe{{[0-9a-z]+}}
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; CHECK-NEXT: v_movreld_b32_e32 v0, v{{[0-9]}}
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; CHECK: s_cbranch_execnz
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define void @insert_neg_offset_vgpr(i32 addrspace(1)* %in, <4 x i32> addrspace(1)* %out) {
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entry:
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%id = call i32 @llvm.r600.read.tidig.x() #1
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%index = add i32 %id, -512
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%value = insertelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 5, i32 %index
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store <4 x i32> %value, <4 x i32> addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}insert_neg_inline_offset_vgpr:
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; The offset depends on the register that holds the first element of the vector.
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; CHECK: v_readfirstlane_b32
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; CHECK: s_add_i32 m0, m0, -{{[0-9]+}}
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; CHECK-NEXT: v_movreld_b32_e32 v0, v{{[0-9]}}
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; CHECK: s_cbranch_execnz
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define void @insert_neg_inline_offset_vgpr(i32 addrspace(1)* %in, <4 x i32> addrspace(1)* %out) {
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entry:
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%id = call i32 @llvm.r600.read.tidig.x() #1
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%index = add i32 %id, -16
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%value = insertelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 5, i32 %index
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store <4 x i32> %value, <4 x i32> addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.r600.read.tidig.x() #1
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attributes #1 = { nounwind readnone }
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