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The intrinsic target prefix should match the target name as it appears in the triple. This is not yet complete, but gets most of the important ones. llvm.AMDGPU.* intrinsics used by mesa and libclc are still handled for compatability for now. llvm-svn: 258557
45 lines
1.7 KiB
LLVM
45 lines
1.7 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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declare float @llvm.amdgcn.ldexp.f32(float, i32) nounwind readnone
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declare double @llvm.amdgcn.ldexp.f64(double, i32) nounwind readnone
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declare float @llvm.AMDGPU.ldexp.f32(float, i32) nounwind readnone
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declare double @llvm.AMDGPU.ldexp.f64(double, i32) nounwind readnone
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; SI-LABEL: {{^}}test_ldexp_f32:
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; SI: v_ldexp_f32
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; SI: s_endpgm
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define void @test_ldexp_f32(float addrspace(1)* %out, float %a, i32 %b) nounwind {
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%result = call float @llvm.amdgcn.ldexp.f32(float %a, i32 %b) nounwind readnone
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store float %result, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_ldexp_f64:
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; SI: v_ldexp_f64
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; SI: s_endpgm
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define void @test_ldexp_f64(double addrspace(1)* %out, double %a, i32 %b) nounwind {
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%result = call double @llvm.amdgcn.ldexp.f64(double %a, i32 %b) nounwind readnone
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store double %result, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL: {{^}}test_legacy_ldexp_f32:
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; SI: v_ldexp_f32
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; SI: s_endpgm
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define void @test_legacy_ldexp_f32(float addrspace(1)* %out, float %a, i32 %b) nounwind {
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%result = call float @llvm.AMDGPU.ldexp.f32(float %a, i32 %b) nounwind readnone
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store float %result, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_legacy_ldexp_f64:
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; SI: v_ldexp_f64
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; SI: s_endpgm
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define void @test_legacy_ldexp_f64(double addrspace(1)* %out, double %a, i32 %b) nounwind {
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%result = call double @llvm.AMDGPU.ldexp.f64(double %a, i32 %b) nounwind readnone
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store double %result, double addrspace(1)* %out, align 8
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ret void
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}
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