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1a1843568a
No tests are included just yet - this is used from the pseudo instruction expander pass, which hasn't been pulled in-tree yet. llvm-svn: 283316
267 lines
8.8 KiB
C++
267 lines
8.8 KiB
C++
//===-- AVRRegisterInfo.cpp - AVR Register Information --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the AVR implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "AVRRegisterInfo.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "AVR.h"
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#include "AVRInstrInfo.h"
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#include "AVRTargetMachine.h"
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#include "MCTargetDesc/AVRMCTargetDesc.h"
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#define GET_REGINFO_TARGET_DESC
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#include "AVRGenRegisterInfo.inc"
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namespace llvm {
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AVRRegisterInfo::AVRRegisterInfo() : AVRGenRegisterInfo(0) {}
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const uint16_t *
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AVRRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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CallingConv::ID CC = MF->getFunction()->getCallingConv();
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return ((CC == CallingConv::AVR_INTR || CC == CallingConv::AVR_SIGNAL)
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? CSR_Interrupts_SaveList
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: CSR_Normal_SaveList);
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}
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const uint32_t *
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AVRRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID CC) const {
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return ((CC == CallingConv::AVR_INTR || CC == CallingConv::AVR_SIGNAL)
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? CSR_Interrupts_RegMask
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: CSR_Normal_RegMask);
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}
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BitVector AVRRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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const AVRTargetMachine &TM = static_cast<const AVRTargetMachine&>(MF.getTarget());
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const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();
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// Reserve the intermediate result registers r1 and r2
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// The result of instructions like 'mul' is always stored here.
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Reserved.set(AVR::R0);
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Reserved.set(AVR::R1);
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Reserved.set(AVR::R1R0);
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// Reserve the stack pointer.
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Reserved.set(AVR::SPL);
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Reserved.set(AVR::SPH);
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Reserved.set(AVR::SP);
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// Reserve the frame pointer registers r28 and r29 if the function requires one.
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if (TFI->hasFP(MF)) {
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Reserved.set(AVR::R28);
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Reserved.set(AVR::R29);
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Reserved.set(AVR::R29R28);
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}
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return Reserved;
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}
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const TargetRegisterClass *
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AVRRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
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const MachineFunction &MF) const {
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if (RC->hasType(MVT::i16)) {
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return &AVR::DREGSRegClass;
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}
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if (RC->hasType(MVT::i8)) {
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return &AVR::GPR8RegClass;
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}
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llvm_unreachable("Invalid register size");
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}
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/// Fold a frame offset shared between two add instructions into a single one.
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static void foldFrameOffset(MachineInstr &MI, int &Offset, unsigned DstReg) {
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int Opcode = MI.getOpcode();
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// Don't bother trying if the next instruction is not an add or a sub.
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if ((Opcode != AVR::SUBIWRdK) && (Opcode != AVR::ADIWRdK)) {
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return;
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}
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// Check that DstReg matches with next instruction, otherwise the instruction
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// is not related to stack address manipulation.
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if (DstReg != MI.getOperand(0).getReg()) {
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return;
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}
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// Add the offset in the next instruction to our offset.
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switch (Opcode) {
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case AVR::SUBIWRdK:
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Offset += -MI.getOperand(2).getImm();
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break;
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case AVR::ADIWRdK:
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Offset += MI.getOperand(2).getImm();
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break;
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}
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// Finally remove the instruction.
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MI.eraseFromParent();
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}
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void AVRRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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assert(SPAdj == 0 && "Unexpected SPAdj value");
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MachineInstr &MI = *II;
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DebugLoc dl = MI.getDebugLoc();
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MachineBasicBlock &MBB = *MI.getParent();
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const MachineFunction &MF = *MBB.getParent();
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const AVRTargetMachine &TM = (const AVRTargetMachine &)MF.getTarget();
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const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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const TargetFrameLowering *TFI = TM.getSubtargetImpl()->getFrameLowering();
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int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
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int Offset = MFI.getObjectOffset(FrameIndex);
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// Add one to the offset because SP points to an empty slot.
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Offset += MFI.getStackSize() - TFI->getOffsetOfLocalArea() + 1;
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// Fold incoming offset.
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Offset += MI.getOperand(FIOperandNum + 1).getImm();
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// This is actually "load effective address" of the stack slot
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// instruction. We have only two-address instructions, thus we need to
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// expand it into move + add.
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if (MI.getOpcode() == AVR::FRMIDX) {
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MI.setDesc(TII.get(AVR::MOVWRdRr));
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MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
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assert(Offset > 0 && "Invalid offset");
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// We need to materialize the offset via an add instruction.
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unsigned Opcode;
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unsigned DstReg = MI.getOperand(0).getReg();
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assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer");
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// Generally, to load a frame address two add instructions are emitted that
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// could get folded into a single one:
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// movw r31:r30, r29:r28
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// adiw r31:r30, 29
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// adiw r31:r30, 16
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// to:
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// movw r31:r30, r29:r28
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// adiw r31:r30, 45
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foldFrameOffset(*std::next(II), Offset, DstReg);
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// Select the best opcode based on DstReg and the offset size.
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switch (DstReg) {
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case AVR::R25R24:
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case AVR::R27R26:
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case AVR::R31R30: {
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if (isUInt<6>(Offset)) {
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Opcode = AVR::ADIWRdK;
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break;
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}
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LLVM_FALLTHROUGH;
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}
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default: {
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// This opcode will get expanded into a pair of subi/sbci.
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Opcode = AVR::SUBIWRdK;
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Offset = -Offset;
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break;
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}
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}
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MachineInstr *New = BuildMI(MBB, std::next(II), dl, TII.get(Opcode), DstReg)
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.addReg(DstReg, RegState::Kill)
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.addImm(Offset);
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New->getOperand(3).setIsDead();
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return;
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}
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// If the offset is too big we have to adjust and restore the frame pointer
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// to materialize a valid load/store with displacement.
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//:TODO: consider using only one adiw/sbiw chain for more than one frame index
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if (Offset >= 63) {
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unsigned AddOpc = AVR::ADIWRdK, SubOpc = AVR::SBIWRdK;
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int AddOffset = Offset - 63 + 1;
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// For huge offsets where adiw/sbiw cannot be used use a pair of subi/sbci.
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if ((Offset - 63 + 1) > 63) {
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AddOpc = AVR::SUBIWRdK;
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SubOpc = AVR::SUBIWRdK;
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AddOffset = -AddOffset;
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}
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// It is possible that the spiller places this frame instruction in between
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// a compare and branch, invalidating the contents of SREG set by the
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// compare instruction because of the add/sub pairs. Conservatively save and
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// restore SREG before and after each add/sub pair.
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BuildMI(MBB, II, dl, TII.get(AVR::INRdA), AVR::R0).addImm(0x3f);
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MachineInstr *New = BuildMI(MBB, II, dl, TII.get(AddOpc), AVR::R29R28)
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.addReg(AVR::R29R28, RegState::Kill)
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.addImm(AddOffset);
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New->getOperand(3).setIsDead();
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// Restore SREG.
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BuildMI(MBB, std::next(II), dl, TII.get(AVR::OUTARr))
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.addImm(0x3f)
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.addReg(AVR::R0, RegState::Kill);
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// No need to set SREG as dead here otherwise if the next instruction is a
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// cond branch it will be using a dead register.
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New = BuildMI(MBB, std::next(II), dl, TII.get(SubOpc), AVR::R29R28)
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.addReg(AVR::R29R28, RegState::Kill)
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.addImm(Offset - 63 + 1);
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Offset = 62;
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}
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MI.getOperand(FIOperandNum).ChangeToRegister(AVR::R29R28, false);
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assert(isUInt<6>(Offset) && "Offset is out of range");
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
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}
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unsigned AVRRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
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if (TFI->hasFP(MF)) {
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// The Y pointer register
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return AVR::R28;
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}
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return AVR::SP;
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}
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const TargetRegisterClass *
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AVRRegisterInfo::getPointerRegClass(const MachineFunction &MF,
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unsigned Kind) const {
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// FIXME: Currently we're using avr-gcc as reference, so we restrict
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// ptrs to Y and Z regs. Though avr-gcc has buggy implementation
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// of memory constraint, so we can fix it and bit avr-gcc here ;-)
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return &AVR::PTRDISPREGSRegClass;
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}
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void AVRRegisterInfo::splitReg(unsigned Reg,
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unsigned &LoReg,
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unsigned &HiReg) const {
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assert(AVR::DREGSRegClass.contains(Reg) && "can only split 16-bit registers");
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LoReg = getSubReg(Reg, AVR::sub_lo);
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HiReg = getSubReg(Reg, AVR::sub_hi);
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}
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} // end of namespace llvm
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