mirror of
https://github.com/RPCS3/llvm-mirror.git
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38e5713f51
Summary: This avoids needing an isel pattern for each condition code. And it removes translation switches for converting between Jcc instructions and condition codes. Now the printer, encoder and disassembler take care of converting the immediate. We use InstAliases to handle the assembly matching. But we print using the asm string in the instruction definition. The instruction itself is marked IsCodeGenOnly=1 to hide it from the assembly parser. Reviewers: spatel, lebedev.ri, courbet, gchatelet, RKSimon Reviewed By: RKSimon Subscribers: MatzeB, qcolombet, eraman, hiraditya, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60228 llvm-svn: 357802
416 lines
20 KiB
TableGen
416 lines
20 KiB
TableGen
//===-- X86InstrControl.td - Control Flow Instructions -----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 jump, return, call, and related instructions.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Control Flow Instructions.
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//
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// Return instructions.
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//
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// The X86retflag return instructions are variadic because we may add ST0 and
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// ST1 arguments when returning values on the x87 stack.
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let isTerminator = 1, isReturn = 1, isBarrier = 1,
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hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
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def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops),
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"ret{l}", []>, OpSize32, Requires<[Not64BitMode]>;
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def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops),
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"ret{q}", []>, OpSize32, Requires<[In64BitMode]>;
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def RETW : I <0xC3, RawFrm, (outs), (ins),
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"ret{w}", []>, OpSize16;
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def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
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"ret{l}\t$amt", []>, OpSize32, Requires<[Not64BitMode]>;
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def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
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"ret{q}\t$amt", []>, OpSize32, Requires<[In64BitMode]>;
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def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
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"ret{w}\t$amt", []>, OpSize16;
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def LRETL : I <0xCB, RawFrm, (outs), (ins),
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"{l}ret{l|f}", []>, OpSize32;
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def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
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"{l}ret{|f}q", []>, Requires<[In64BitMode]>;
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def LRETW : I <0xCB, RawFrm, (outs), (ins),
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"{l}ret{w|f}", []>, OpSize16;
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def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
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"{l}ret{l|f}\t$amt", []>, OpSize32;
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def LRETIQ : RIi16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
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"{l}ret{|f}q\t$amt", []>, Requires<[In64BitMode]>;
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def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
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"{l}ret{w|f}\t$amt", []>, OpSize16;
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// The machine return from interrupt instruction, but sometimes we need to
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// perform a post-epilogue stack adjustment. Codegen emits the pseudo form
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// which expands to include an SP adjustment if necessary.
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def IRET16 : I <0xcf, RawFrm, (outs), (ins), "iret{w}", []>,
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OpSize16;
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def IRET32 : I <0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>, OpSize32;
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def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>;
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let isCodeGenOnly = 1 in
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def IRET : PseudoI<(outs), (ins i32imm:$adj), [(X86iret timm:$adj)]>;
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def RET : PseudoI<(outs), (ins i32imm:$adj, variable_ops), [(X86retflag timm:$adj)]>;
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}
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// Unconditional branches.
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let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
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def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
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"jmp\t$dst", [(br bb:$dst)]>;
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let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in {
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def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget16:$dst),
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"jmp\t$dst", []>, OpSize16;
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def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget32:$dst),
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"jmp\t$dst", []>, OpSize32;
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}
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}
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// Conditional Branches.
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let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump],
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isCodeGenOnly = 1, ForceDisassemble = 1 in {
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def JCC_1 : Ii8PCRel <0x70, AddCCFrm, (outs),
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(ins brtarget8:$dst, ccode:$cond),
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"j${cond}\t$dst",
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[(X86brcond bb:$dst, imm:$cond, EFLAGS)]>;
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let hasSideEffects = 0 in {
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def JCC_2 : Ii16PCRel<0x80, AddCCFrm, (outs),
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(ins brtarget16:$dst, ccode:$cond),
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"j${cond}\t$dst",
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[]>, OpSize16, TB;
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def JCC_4 : Ii32PCRel<0x80, AddCCFrm, (outs),
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(ins brtarget32:$dst, ccode:$cond),
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"j${cond}\t$dst",
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[]>, TB, OpSize32;
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}
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}
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def : InstAlias<"jo\t$dst", (JCC_1 brtarget8:$dst, 0), 0>;
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def : InstAlias<"jno\t$dst", (JCC_1 brtarget8:$dst, 1), 0>;
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def : InstAlias<"jb\t$dst", (JCC_1 brtarget8:$dst, 2), 0>;
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def : InstAlias<"jae\t$dst", (JCC_1 brtarget8:$dst, 3), 0>;
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def : InstAlias<"je\t$dst", (JCC_1 brtarget8:$dst, 4), 0>;
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def : InstAlias<"jne\t$dst", (JCC_1 brtarget8:$dst, 5), 0>;
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def : InstAlias<"jbe\t$dst", (JCC_1 brtarget8:$dst, 6), 0>;
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def : InstAlias<"ja\t$dst", (JCC_1 brtarget8:$dst, 7), 0>;
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def : InstAlias<"js\t$dst", (JCC_1 brtarget8:$dst, 8), 0>;
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def : InstAlias<"jns\t$dst", (JCC_1 brtarget8:$dst, 9), 0>;
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def : InstAlias<"jp\t$dst", (JCC_1 brtarget8:$dst, 10), 0>;
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def : InstAlias<"jnp\t$dst", (JCC_1 brtarget8:$dst, 11), 0>;
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def : InstAlias<"jl\t$dst", (JCC_1 brtarget8:$dst, 12), 0>;
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def : InstAlias<"jge\t$dst", (JCC_1 brtarget8:$dst, 13), 0>;
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def : InstAlias<"jle\t$dst", (JCC_1 brtarget8:$dst, 14), 0>;
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def : InstAlias<"jg\t$dst", (JCC_1 brtarget8:$dst, 15), 0>;
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// jcx/jecx/jrcx instructions.
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let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in {
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// These are the 32-bit versions of this instruction for the asmparser. In
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// 32-bit mode, the address size prefix is jcxz and the unprefixed version is
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// jecxz.
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let Uses = [CX] in
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def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
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"jcxz\t$dst", []>, AdSize16, Requires<[Not64BitMode]>;
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let Uses = [ECX] in
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def JECXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
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"jecxz\t$dst", []>, AdSize32;
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let Uses = [RCX] in
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def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
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"jrcxz\t$dst", []>, AdSize64, Requires<[In64BitMode]>;
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}
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// Indirect branches
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let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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def JMP16r : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst",
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[(brind GR16:$dst)]>, Requires<[Not64BitMode]>,
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OpSize16, Sched<[WriteJump]>;
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def JMP16m : I<0xFF, MRM4m, (outs), (ins i16mem:$dst), "jmp{w}\t{*}$dst",
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[(brind (loadi16 addr:$dst))]>, Requires<[Not64BitMode]>,
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OpSize16, Sched<[WriteJumpLd]>;
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def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
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[(brind GR32:$dst)]>, Requires<[Not64BitMode]>,
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OpSize32, Sched<[WriteJump]>;
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def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
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[(brind (loadi32 addr:$dst))]>, Requires<[Not64BitMode]>,
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OpSize32, Sched<[WriteJumpLd]>;
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def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
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[(brind GR64:$dst)]>, Requires<[In64BitMode]>,
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Sched<[WriteJump]>;
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def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
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[(brind (loadi64 addr:$dst))]>, Requires<[In64BitMode]>,
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Sched<[WriteJumpLd]>;
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// Non-tracking jumps for IBT, use with caution.
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let isCodeGenOnly = 1 in {
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def JMP16r_NT : I<0xFF, MRM4r, (outs), (ins GR16 : $dst), "jmp{w}\t{*}$dst",
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[(X86NoTrackBrind GR16 : $dst)]>, Requires<[Not64BitMode]>,
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OpSize16, Sched<[WriteJump]>, NOTRACK;
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def JMP16m_NT : I<0xFF, MRM4m, (outs), (ins i16mem : $dst), "jmp{w}\t{*}$dst",
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[(X86NoTrackBrind (loadi16 addr : $dst))]>,
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Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>,
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NOTRACK;
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def JMP32r_NT : I<0xFF, MRM4r, (outs), (ins GR32 : $dst), "jmp{l}\t{*}$dst",
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[(X86NoTrackBrind GR32 : $dst)]>, Requires<[Not64BitMode]>,
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OpSize32, Sched<[WriteJump]>, NOTRACK;
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def JMP32m_NT : I<0xFF, MRM4m, (outs), (ins i32mem : $dst), "jmp{l}\t{*}$dst",
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[(X86NoTrackBrind (loadi32 addr : $dst))]>,
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Requires<[Not64BitMode]>, OpSize32, Sched<[WriteJumpLd]>,
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NOTRACK;
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def JMP64r_NT : I<0xFF, MRM4r, (outs), (ins GR64 : $dst), "jmp{q}\t{*}$dst",
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[(X86NoTrackBrind GR64 : $dst)]>, Requires<[In64BitMode]>,
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Sched<[WriteJump]>, NOTRACK;
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def JMP64m_NT : I<0xFF, MRM4m, (outs), (ins i64mem : $dst), "jmp{q}\t{*}$dst",
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[(X86NoTrackBrind(loadi64 addr : $dst))]>,
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Requires<[In64BitMode]>, Sched<[WriteJumpLd]>, NOTRACK;
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}
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let Predicates = [Not64BitMode], AsmVariantName = "att" in {
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def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
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(ins i16imm:$off, i16imm:$seg),
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"ljmp{w}\t$seg, $off", []>,
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OpSize16, Sched<[WriteJump]>;
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def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
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(ins i32imm:$off, i16imm:$seg),
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"ljmp{l}\t$seg, $off", []>,
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OpSize32, Sched<[WriteJump]>;
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}
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def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaquemem:$dst),
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"ljmp{q}\t{*}$dst", []>, Sched<[WriteJump]>, Requires<[In64BitMode]>;
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let AsmVariantName = "att" in
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def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst),
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"ljmp{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>;
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def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst),
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"{l}jmp{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>;
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}
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// Loop instructions
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let SchedRW = [WriteJump] in {
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def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>;
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def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>;
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def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>;
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}
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//===----------------------------------------------------------------------===//
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// Call Instructions...
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//
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let isCall = 1 in
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// All calls clobber the non-callee saved registers. ESP is marked as
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// a use to prevent stack-pointer assignments that appear immediately
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// before calls from potentially appearing dead. Uses for argument
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// registers are added manually.
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let Uses = [ESP, SSP] in {
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def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
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(outs), (ins i32imm_pcrel:$dst),
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"call{l}\t$dst", []>, OpSize32,
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Requires<[Not64BitMode]>, Sched<[WriteJump]>;
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let hasSideEffects = 0 in
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def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
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(outs), (ins i16imm_pcrel:$dst),
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"call{w}\t$dst", []>, OpSize16,
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Sched<[WriteJump]>;
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def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst),
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"call{w}\t{*}$dst", [(X86call GR16:$dst)]>,
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OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
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def CALL16m : I<0xFF, MRM2m, (outs), (ins i16mem:$dst),
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"call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))]>,
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OpSize16, Requires<[Not64BitMode,FavorMemIndirectCall]>,
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Sched<[WriteJumpLd]>;
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def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
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"call{l}\t{*}$dst", [(X86call GR32:$dst)]>, OpSize32,
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Requires<[Not64BitMode,NotUseRetpolineIndirectCalls]>,
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Sched<[WriteJump]>;
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def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),
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"call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))]>,
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OpSize32,
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Requires<[Not64BitMode,FavorMemIndirectCall,
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NotUseRetpolineIndirectCalls]>,
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Sched<[WriteJumpLd]>;
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// Non-tracking calls for IBT, use with caution.
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let isCodeGenOnly = 1 in {
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def CALL16r_NT : I<0xFF, MRM2r, (outs), (ins GR16 : $dst),
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"call{w}\t{*}$dst",[(X86NoTrackCall GR16 : $dst)]>,
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OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>, NOTRACK;
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def CALL16m_NT : I<0xFF, MRM2m, (outs), (ins i16mem : $dst),
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"call{w}\t{*}$dst",[(X86NoTrackCall(loadi16 addr : $dst))]>,
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OpSize16, Requires<[Not64BitMode,FavorMemIndirectCall]>,
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Sched<[WriteJumpLd]>, NOTRACK;
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def CALL32r_NT : I<0xFF, MRM2r, (outs), (ins GR32 : $dst),
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"call{l}\t{*}$dst",[(X86NoTrackCall GR32 : $dst)]>,
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OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>, NOTRACK;
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def CALL32m_NT : I<0xFF, MRM2m, (outs), (ins i32mem : $dst),
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"call{l}\t{*}$dst",[(X86NoTrackCall(loadi32 addr : $dst))]>,
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OpSize32, Requires<[Not64BitMode,FavorMemIndirectCall]>,
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Sched<[WriteJumpLd]>, NOTRACK;
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}
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let Predicates = [Not64BitMode], AsmVariantName = "att" in {
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def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
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(ins i16imm:$off, i16imm:$seg),
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"lcall{w}\t$seg, $off", []>,
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OpSize16, Sched<[WriteJump]>;
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def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
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(ins i32imm:$off, i16imm:$seg),
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"lcall{l}\t$seg, $off", []>,
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OpSize32, Sched<[WriteJump]>;
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}
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def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst),
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"lcall{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>;
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def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst),
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"{l}call{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>;
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}
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// Tail call stuff.
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
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isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in
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let Uses = [ESP, SSP] in {
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def TCRETURNdi : PseudoI<(outs),
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(ins i32imm_pcrel:$dst, i32imm:$offset), []>, NotMemoryFoldable;
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def TCRETURNri : PseudoI<(outs),
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(ins ptr_rc_tailcall:$dst, i32imm:$offset), []>, NotMemoryFoldable;
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let mayLoad = 1 in
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def TCRETURNmi : PseudoI<(outs),
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(ins i32mem_TC:$dst, i32imm:$offset), []>;
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// FIXME: The should be pseudo instructions that are lowered when going to
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// mcinst.
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def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
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(ins i32imm_pcrel:$dst), "jmp\t$dst", []>;
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def TAILJMPr : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
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"", []>; // FIXME: Remove encoding when JIT is dead.
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let mayLoad = 1 in
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def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst),
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"jmp{l}\t{*}$dst", []>;
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}
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// Conditional tail calls are similar to the above, but they are branches
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// rather than barriers, and they use EFLAGS.
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let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1,
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isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in
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let Uses = [ESP, EFLAGS, SSP] in {
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def TCRETURNdicc : PseudoI<(outs),
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(ins i32imm_pcrel:$dst, i32imm:$offset, i32imm:$cond), []>;
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// This gets substituted to a conditional jump instruction in MC lowering.
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def TAILJMPd_CC : Ii32PCRel<0x80, RawFrm, (outs),
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(ins i32imm_pcrel:$dst, i32imm:$cond), "", []>;
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}
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//===----------------------------------------------------------------------===//
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// Call Instructions...
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//
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// RSP is marked as a use to prevent stack-pointer assignments that appear
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// immediately before calls from potentially appearing dead. Uses for argument
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// registers are added manually.
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let isCall = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in {
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// NOTE: this pattern doesn't match "X86call imm", because we do not know
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// that the offset between an arbitrary immediate and the call will fit in
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// the 32-bit pcrel field that we have.
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def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
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(outs), (ins i64i32imm_pcrel:$dst),
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"call{q}\t$dst", []>, OpSize32,
|
|
Requires<[In64BitMode]>;
|
|
def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst),
|
|
"call{q}\t{*}$dst", [(X86call GR64:$dst)]>,
|
|
Requires<[In64BitMode,NotUseRetpolineIndirectCalls]>;
|
|
def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst),
|
|
"call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
|
|
Requires<[In64BitMode,FavorMemIndirectCall,
|
|
NotUseRetpolineIndirectCalls]>;
|
|
|
|
// Non-tracking calls for IBT, use with caution.
|
|
let isCodeGenOnly = 1 in {
|
|
def CALL64r_NT : I<0xFF, MRM2r, (outs), (ins GR64 : $dst),
|
|
"call{q}\t{*}$dst",[(X86NoTrackCall GR64 : $dst)]>,
|
|
Requires<[In64BitMode]>, NOTRACK;
|
|
def CALL64m_NT : I<0xFF, MRM2m, (outs), (ins i64mem : $dst),
|
|
"call{q}\t{*}$dst",
|
|
[(X86NoTrackCall(loadi64 addr : $dst))]>,
|
|
Requires<[In64BitMode,FavorMemIndirectCall]>, NOTRACK;
|
|
}
|
|
|
|
def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaquemem:$dst),
|
|
"lcall{q}\t{*}$dst", []>;
|
|
}
|
|
|
|
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
|
|
isCodeGenOnly = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in {
|
|
def TCRETURNdi64 : PseudoI<(outs),
|
|
(ins i64i32imm_pcrel:$dst, i32imm:$offset),
|
|
[]>;
|
|
def TCRETURNri64 : PseudoI<(outs),
|
|
(ins ptr_rc_tailcall:$dst, i32imm:$offset), []>, NotMemoryFoldable;
|
|
let mayLoad = 1 in
|
|
def TCRETURNmi64 : PseudoI<(outs),
|
|
(ins i64mem_TC:$dst, i32imm:$offset), []>, NotMemoryFoldable;
|
|
|
|
def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs), (ins i64i32imm_pcrel:$dst),
|
|
"jmp\t$dst", []>;
|
|
|
|
def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
|
|
"jmp{q}\t{*}$dst", []>;
|
|
|
|
let mayLoad = 1 in
|
|
def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst),
|
|
"jmp{q}\t{*}$dst", []>;
|
|
|
|
// Win64 wants indirect jumps leaving the function to have a REX_W prefix.
|
|
let hasREX_WPrefix = 1 in {
|
|
def TAILJMPr64_REX : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
|
|
"rex64 jmp{q}\t{*}$dst", []>;
|
|
|
|
let mayLoad = 1 in
|
|
def TAILJMPm64_REX : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst),
|
|
"rex64 jmp{q}\t{*}$dst", []>;
|
|
}
|
|
}
|
|
|
|
let isPseudo = 1, isCall = 1, isCodeGenOnly = 1,
|
|
Uses = [RSP, SSP],
|
|
usesCustomInserter = 1,
|
|
SchedRW = [WriteJump] in {
|
|
def RETPOLINE_CALL32 :
|
|
PseudoI<(outs), (ins GR32:$dst), [(X86call GR32:$dst)]>,
|
|
Requires<[Not64BitMode,UseRetpolineIndirectCalls]>;
|
|
|
|
def RETPOLINE_CALL64 :
|
|
PseudoI<(outs), (ins GR64:$dst), [(X86call GR64:$dst)]>,
|
|
Requires<[In64BitMode,UseRetpolineIndirectCalls]>;
|
|
|
|
// Retpoline variant of indirect tail calls.
|
|
let isTerminator = 1, isReturn = 1, isBarrier = 1 in {
|
|
def RETPOLINE_TCRETURN64 :
|
|
PseudoI<(outs), (ins GR64:$dst, i32imm:$offset), []>;
|
|
def RETPOLINE_TCRETURN32 :
|
|
PseudoI<(outs), (ins GR32:$dst, i32imm:$offset), []>;
|
|
}
|
|
}
|
|
|
|
// Conditional tail calls are similar to the above, but they are branches
|
|
// rather than barriers, and they use EFLAGS.
|
|
let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1,
|
|
isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in
|
|
let Uses = [RSP, EFLAGS, SSP] in {
|
|
def TCRETURNdi64cc : PseudoI<(outs),
|
|
(ins i64i32imm_pcrel:$dst, i32imm:$offset,
|
|
i32imm:$cond), []>;
|
|
|
|
// This gets substituted to a conditional jump instruction in MC lowering.
|
|
def TAILJMPd64_CC : Ii32PCRel<0x80, RawFrm, (outs),
|
|
(ins i64i32imm_pcrel:$dst, i32imm:$cond), "", []>;
|
|
}
|