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58f2da5889
We were generating "fmov h0, wzr" instructions when FullFP16 is not enabled. I've not added any tests, because the problem was visible in: test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll, which I had to change: I don't think Cyclone has FullFP16 enabled by default, so it shouldn't be using this v8.2a instruction. I've also removed these rdar tags, please shout if there are any objections. Differential Revision: https://reviews.llvm.org/D43020 llvm-svn: 324581
98 lines
3.0 KiB
LLVM
98 lines
3.0 KiB
LLVM
; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone < %s | FileCheck %s -check-prefixes=ALL,CYCLONE
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; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone -mattr=+fullfp16 < %s | FileCheck %s -check-prefixes=CYCLONE-FULLFP16
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; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=exynos-m1 < %s | FileCheck %s -check-prefixes=ALL,OTHERS
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; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=exynos-m3 < %s | FileCheck %s -check-prefixes=ALL,OTHERS
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; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=kryo < %s | FileCheck %s -check-prefixes=ALL,OTHERS
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; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=falkor < %s | FileCheck %s -check-prefixes=ALL,OTHERS
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declare void @bar(half, float, double, <2 x double>)
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declare void @bari(i32, i32)
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declare void @barl(i64, i64)
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declare void @barf(float, float)
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define void @t1() nounwind ssp {
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entry:
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; ALL-LABEL: t1:
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; ALL-NOT: fmov
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; ALL: ldr h0,{{.*}}
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; CYCLONE: fmov s1, wzr
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; CYCLONE: fmov d2, xzr
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; CYCLONE: movi.16b v3, #0
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; CYCLONE-FULLFP16: fmov h0, wzr
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; CYCLONE-FULLFP16: fmov s1, wzr
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; CYCLONE-FULLFP16: fmov d2, xzr
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; CYCLONE-FULLFP16: movi.16b v3, #0
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; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
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; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
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; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
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tail call void @bar(half 0.000000e+00, float 0.000000e+00, double 0.000000e+00, <2 x double> <double 0.000000e+00, double 0.000000e+00>) nounwind
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ret void
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}
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define void @t2() nounwind ssp {
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entry:
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; ALL-LABEL: t2:
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; ALL-NOT: mov w0, wzr
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; ALL: mov w{{[0-3]+}}, #0
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; ALL: mov w{{[0-3]+}}, #0
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tail call void @bari(i32 0, i32 0) nounwind
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ret void
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}
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define void @t3() nounwind ssp {
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entry:
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; ALL-LABEL: t3:
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; ALL-NOT: mov x0, xzr
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; ALL: mov x{{[0-3]+}}, #0
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; ALL: mov x{{[0-3]+}}, #0
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tail call void @barl(i64 0, i64 0) nounwind
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ret void
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}
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define void @t4() nounwind ssp {
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; ALL-LABEL: t4:
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; ALL-NOT: fmov
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; CYCLONE: fmov s{{[0-3]+}}, wzr
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; CYCLONE: fmov s{{[0-3]+}}, wzr
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; CYCLONE-FULLFP16: fmov s{{[0-3]+}}, wzr
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; CYCLONE-FULLFP16: fmov s{{[0-3]+}}, wzr
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; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
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; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
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tail call void @barf(float 0.000000e+00, float 0.000000e+00) nounwind
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ret void
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}
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; We used to produce spills+reloads for a Q register with zero cycle zeroing
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; enabled.
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; ALL-LABEL: foo:
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; ALL-NOT: str q{{[0-9]+}}
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; ALL-NOT: ldr q{{[0-9]+}}
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define double @foo(i32 %n) {
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entry:
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br label %for.body
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for.body:
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%phi0 = phi double [ 1.0, %entry ], [ %v0, %for.body ]
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%i.076 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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%conv21 = sitofp i32 %i.076 to double
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%call = tail call fast double @sin(double %conv21)
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%cmp.i = fcmp fast olt double %phi0, %call
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%v0 = select i1 %cmp.i, double %call, double %phi0
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%inc = add nuw nsw i32 %i.076, 1
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%cmp = icmp slt i32 %inc, %n
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br i1 %cmp, label %for.body, label %for.end
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for.end:
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ret double %v0
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}
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define <2 x i64> @t6() {
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; ALL-LABEL: t6:
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; CYCLONE: movi.16b v0, #0
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; OTHERS: movi v0.2d, #0000000000000000
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ret <2 x i64> zeroinitializer
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}
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declare double @sin(double)
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