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d42b05387d
Reenable post-legalize stores with constant merging computation and corresponding test case. * Properly truncate store merge constants * Disable merging of truncated stores floating points * Ensure merges of constant stores into a single vector are constructed from legal elements. Reviewers: eastig, efriedma Reviewed By: eastig Subscribers: spatel, rengolin, aemerson, javed.absar, kristof.beyls, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40701 llvm-svn: 319899
47 lines
1.4 KiB
LLVM
47 lines
1.4 KiB
LLVM
; RUN: llc < %s -mtriple arm64-apple-darwin -aarch64-enable-ldst-opt=false -disable-post-ra -asm-verbose=false | FileCheck %s
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; Disable the load/store optimizer to avoid having LDP/STPs and simplify checks.
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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; Check that we don't try to tail-call with an sret-demoted return.
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declare i1024 @test_sret() #0
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; CHECK-LABEL: _test_call_sret:
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; CHECK: mov x[[CALLERX8NUM:[0-9]+]], x8
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; CHECK: mov x8, sp
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; CHECK-NEXT: bl _test_sret
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; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp]
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; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]]
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; CHECK: ret
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define i1024 @test_call_sret() #0 {
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%a = call i1024 @test_sret()
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ret i1024 %a
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}
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; CHECK-LABEL: _test_tailcall_sret:
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; CHECK: mov x[[CALLERX8NUM:[0-9]+]], x8
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; CHECK: mov x8, sp
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; CHECK-NEXT: bl _test_sret
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; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp]
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; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]]
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; CHECK: ret
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define i1024 @test_tailcall_sret() #0 {
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%a = tail call i1024 @test_sret()
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ret i1024 %a
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}
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; CHECK-LABEL: _test_indirect_tailcall_sret:
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; CHECK: mov x[[CALLERX8NUM:[0-9]+]], x8
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; CHECK: mov x8, sp
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; CHECK-NEXT: blr x0
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; CHECK: ldr [[CALLERSRET1:q[0-9]+]], [sp]
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; CHECK: str [[CALLERSRET1:q[0-9]+]], [x[[CALLERX8NUM]]]
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; CHECK: ret
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define i1024 @test_indirect_tailcall_sret(i1024 ()* %f) #0 {
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%a = tail call i1024 %f()
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ret i1024 %a
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}
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attributes #0 = { nounwind }
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