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llvm-mirror/test/MC/Mips/mt/invalid.s
Simon Dardis 61a86474b9 Reland "[mips][mt][6/7] Add support for mftr, mttr instructions."
This adjusts the tests to hopfully pacify the
llvm-clang-x86_64-expensive-checks-win buildbot.

Unlike many other instructions, these instructions have aliases which
take coprocessor registers, gpr register, accumulator (and dsp accumulator)
registers, floating point registers, floating point control registers and
coprocessor 2 data and control operands.

For the moment, these aliases are treated as pseudo instructions which are
expanded into the underlying instruction. As a result, disassembling these
instructions shows the underlying instruction and not the alias.

Reviewers: slthakur, atanasyan

Differential Revision: https://reviews.llvm.org/D35253

llvm-svn: 318207
2017-11-14 22:26:42 +00:00

16 lines
1015 B
ArmAsm

# RUN: not llvm-mc -arch=mips -mcpu=mips32 -mattr=+mt < %s 2>%t1
# RUN: FileCheck %s < %t1
dmt 4 # CHECK: error: invalid operand for instruction
dmt $4, $5 # CHECK: error: invalid operand for instruction
dmt $5, 0($4) # CHECK: error: invalid operand for instruction
emt 4 # CHECK: error: invalid operand for instruction
emt $4, $5 # CHECK: error: invalid operand for instruction
emt $5, 0($5) # CHECK: error: invalid operand for instruction
dvpe 4 # CHECK: error: invalid operand for instruction
dvpe $4, $5 # CHECK: error: invalid operand for instruction
dvpe $5, 0($4) # CHECK: error: invalid operand for instruction
evpe 4 # CHECK: error: invalid operand for instruction
evpe $4, $5 # CHECK: error: invalid operand for instruction
evpe $5, 0($5) # CHECK: error: invalid operand for instruction
# FIXME: add tests for mftr/mttr.