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620fd19798
llvm-mirror/test/CodeGen
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Evan Cheng 620fd19798 Experimental scheduler change to schedule / coalesce the copies added for function livein's. Take 2008-03-10-RegAllocInfLoop.ll, the schedule looks like this after these copies are inserted: 
entry: 0x12049d0, LLVM BB @0x1201fd0, ID#0:
Live Ins: %EAX %EDX %ECX
        %reg1031<def> = MOVPC32r 0
        %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
        %reg1028<def> = MOV32rr %EAX
        %reg1029<def> = MOV32rr %EDX
        %reg1030<def> = MOV32rr %ECX
        %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x1201910 + 0]
        %reg1025<def> = MOV32rr %reg1029
        %reg1026<def> = MOV32rr %reg1030
        %reg1024<def> = MOV32rr %reg1028

The copies unnecessarily increase register pressure and it will end up requiring a physical register to be spilled.

With -schedule-livein-copies:
entry: 0x12049d0, LLVM BB @0x1201fa0, ID#0:
Live Ins: %EAX %EDX %ECX
        %reg1031<def> = MOVPC32r 0
        %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
        %reg1024<def> = MOV32rr %EAX
        %reg1025<def> = MOV32rr %EDX
        %reg1026<def> = MOV32rr %ECX
        %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x12018e0 + 0]

Much better!

llvm-svn: 48307
2008-03-12 22:19:41 +00:00
..
Alpha Fix RUN line. 2008-03-09 19:55:22 +00:00
ARM Fixed a register scavenger bug. If a def is re-defining part of a super register, there must be an implicit def of the super-register on the MI. 2008-03-07 20:12:54 +00:00
CBackend remove an execution test. 2008-03-10 06:53:14 +00:00
CellSPU - Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency. 2008-03-10 23:49:09 +00:00
Generic Make this test x86-specific for now; targets that don't use 2008-03-12 00:25:14 +00:00
IA64 Remove llvm-upgrade and update tests. 2008-02-19 01:41:04 +00:00
PowerPC The feature this is testing did not work in the general case, 2008-03-11 17:48:26 +00:00
SPARC Remove llvm-upgrade and update tests. 2008-02-19 01:41:04 +00:00
X86 Experimental scheduler change to schedule / coalesce the copies added for function livein's. Take 2008-03-10-RegAllocInfLoop.ll, the schedule looks like this after these copies are inserted: 2008-03-12 22:19:41 +00:00