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https://github.com/RPCS3/llvm-mirror.git
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bab22f59b9
Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175753
300 lines
9.7 KiB
TableGen
300 lines
9.7 KiB
TableGen
//===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// SI DAG Nodes
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//===----------------------------------------------------------------------===//
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// SMRD takes a 64bit memory address and can only add an 32bit offset
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def SIadd64bit32bit : SDNode<"ISD::ADD",
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SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisVT<0, i64>, SDTCisVT<2, i32>]>
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>;
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// Transformation function, extract the lower 32bit of a 64bit immediate
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def LO32 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
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}]>;
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// Transformation function, extract the upper 32bit of a 64bit immediate
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def HI32 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
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}]>;
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def IMM8bitDWORD : ImmLeaf <
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i32, [{
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return (Imm & ~0x3FC) == 0;
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}], SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(
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N->getZExtValue() >> 2, MVT::i32);
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}]>
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>;
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def IMM12bit : ImmLeaf <
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i16,
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[{return isUInt<12>(Imm);}]
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>;
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class InlineImm <ValueType vt> : ImmLeaf <vt, [{
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return -16 <= Imm && Imm <= 64;
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}]>;
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//===----------------------------------------------------------------------===//
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// SI assembler operands
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//===----------------------------------------------------------------------===//
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def SIOperand {
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int ZERO = 0x80;
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}
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class GPR4Align <RegisterClass rc> : Operand <vAny> {
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let EncoderMethod = "GPR4AlignEncode";
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let MIOperandInfo = (ops rc:$reg);
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}
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class GPR2Align <RegisterClass rc> : Operand <iPTR> {
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let EncoderMethod = "GPR2AlignEncode";
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let MIOperandInfo = (ops rc:$reg);
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}
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include "SIInstrFormats.td"
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//===----------------------------------------------------------------------===//
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//
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// SI Instruction multiclass helpers.
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//
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// Instructions with _32 take 32-bit operands.
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// Instructions with _64 take 64-bit operands.
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//
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// VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
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// encoding is the standard encoding, but instruction that make use of
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// any of the instruction modifiers must use the 64-bit encoding.
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//
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// Instructions with _e32 use the 32-bit encoding.
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// Instructions with _e64 use the 64-bit encoding.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Scalar classes
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//===----------------------------------------------------------------------===//
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class SOP1_32 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
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op, (outs SReg_32:$dst), (ins SSrc_32:$src0),
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opName#" $dst, $src0", pattern
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>;
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class SOP1_64 <bits<8> op, string opName, list<dag> pattern> : SOP1 <
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op, (outs SReg_64:$dst), (ins SSrc_64:$src0),
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opName#" $dst, $src0", pattern
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>;
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class SOP2_32 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
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op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
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opName#" $dst, $src0, $src1", pattern
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>;
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class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <
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op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
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opName#" $dst, $src0, $src1", pattern
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>;
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class SOPC_32 <bits<7> op, string opName, list<dag> pattern> : SOPC <
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op, (outs SCCReg:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
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opName#" $dst, $src0, $src1", pattern
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>;
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class SOPC_64 <bits<7> op, string opName, list<dag> pattern> : SOPC <
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op, (outs SCCReg:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
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opName#" $dst, $src0, $src1", pattern
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>;
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class SOPK_32 <bits<5> op, string opName, list<dag> pattern> : SOPK <
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op, (outs SReg_32:$dst), (ins i16imm:$src0),
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opName#" $dst, $src0", pattern
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>;
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class SOPK_64 <bits<5> op, string opName, list<dag> pattern> : SOPK <
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op, (outs SReg_64:$dst), (ins i16imm:$src0),
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opName#" $dst, $src0", pattern
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>;
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multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass> {
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def _IMM : SMRD <
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op, 1, (outs dstClass:$dst),
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(ins GPR2Align<SReg_64>:$sbase, i32imm:$offset),
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asm#" $dst, $sbase, $offset", []
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>;
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def _SGPR : SMRD <
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op, 0, (outs dstClass:$dst),
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(ins GPR2Align<SReg_64>:$sbase, SReg_32:$soff),
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asm#" $dst, $sbase, $soff", []
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>;
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}
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//===----------------------------------------------------------------------===//
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// Vector ALU classes
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//===----------------------------------------------------------------------===//
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multiclass VOP1_Helper <bits<8> op, RegisterClass drc, RegisterClass src,
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string opName, list<dag> pattern> {
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def _e32: VOP1 <
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op, (outs drc:$dst), (ins src:$src0),
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opName#"_e32 $dst, $src0", pattern
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>;
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def _e64 : VOP3 <
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{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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(outs drc:$dst),
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(ins src:$src0,
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i32imm:$abs, i32imm:$clamp,
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i32imm:$omod, i32imm:$neg),
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opName#"_e64 $dst, $src0, $abs, $clamp, $omod, $neg", []
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> {
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let SRC1 = SIOperand.ZERO;
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let SRC2 = SIOperand.ZERO;
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}
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}
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multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern>
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: VOP1_Helper <op, VReg_32, VSrc_32, opName, pattern>;
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multiclass VOP1_64 <bits<8> op, string opName, list<dag> pattern>
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: VOP1_Helper <op, VReg_64, VSrc_64, opName, pattern>;
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multiclass VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
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string opName, list<dag> pattern> {
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def _e32 : VOP2 <
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op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1),
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opName#"_e32 $dst, $src0, $src1", pattern
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>;
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def _e64 : VOP3 <
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{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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(outs vrc:$dst),
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(ins arc:$src0, vrc:$src1,
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i32imm:$abs, i32imm:$clamp,
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i32imm:$omod, i32imm:$neg),
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opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", []
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> {
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let SRC2 = SIOperand.ZERO;
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}
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}
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multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern>
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: VOP2_Helper <op, VReg_32, VSrc_32, opName, pattern>;
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multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern>
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: VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern>;
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multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
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string opName, ValueType vt, PatLeaf cond> {
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def _e32 : VOPC <
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op, (ins arc:$src0, vrc:$src1),
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opName#"_e32 $dst, $src0, $src1", []
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>;
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def _e64 : VOP3 <
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{0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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(outs SReg_64:$dst),
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(ins arc:$src0, vrc:$src1,
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InstFlag:$abs, InstFlag:$clamp,
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InstFlag:$omod, InstFlag:$neg),
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opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg",
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!if(!eq(!cast<string>(cond), "COND_NULL"), []<dag>,
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[(set SReg_64:$dst, (i1 (setcc (vt arc:$src0), vrc:$src1, cond)))]
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)
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> {
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let SRC2 = SIOperand.ZERO;
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}
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}
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multiclass VOPC_32 <bits<8> op, string opName,
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ValueType vt = untyped, PatLeaf cond = COND_NULL>
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: VOPC_Helper <op, VReg_32, VSrc_32, opName, vt, cond>;
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multiclass VOPC_64 <bits<8> op, string opName,
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ValueType vt = untyped, PatLeaf cond = COND_NULL>
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: VOPC_Helper <op, VReg_64, VSrc_64, opName, vt, cond>;
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class VOP3_32 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
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op, (outs VReg_32:$dst),
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(ins VSrc_32:$src0, VReg_32:$src1, VReg_32:$src2,
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i32imm:$abs, i32imm:$clamp, i32imm:$omod, i32imm:$neg),
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opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern
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>;
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class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
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op, (outs VReg_64:$dst),
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(ins VSrc_64:$src0, VReg_64:$src1, VReg_64:$src2,
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i32imm:$abs, i32imm:$clamp, i32imm:$omod, i32imm:$neg),
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opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern
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>;
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//===----------------------------------------------------------------------===//
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// Vector I/O classes
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//===----------------------------------------------------------------------===//
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class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
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op,
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(outs),
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(ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
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i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
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GPR4Align<SReg_128>:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
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asm#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
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#" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
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[]> {
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let mayStore = 1;
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let mayLoad = 0;
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}
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class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
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op,
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(outs regClass:$dst),
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(ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
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i1imm:$lds, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc, i1imm:$slc,
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i1imm:$tfe, SSrc_32:$soffset),
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asm#" $dst, $offset, $offen, $idxen, $glc, $addr64, "
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#"$lds, $vaddr, $srsrc, $slc, $tfe, $soffset",
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[]> {
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let mayLoad = 1;
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let mayStore = 0;
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}
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class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
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op,
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(outs regClass:$dst),
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(ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
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i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc,
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i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
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asm#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
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#" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset",
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[]> {
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let mayLoad = 1;
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let mayStore = 0;
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}
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class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
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op,
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(outs VReg_128:$vdata),
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(ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
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i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_32:$vaddr,
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GPR4Align<SReg_256>:$srsrc, GPR4Align<SReg_128>:$ssamp),
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asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
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#" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
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[]> {
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let mayLoad = 1;
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let mayStore = 0;
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}
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include "SIInstructions.td"
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