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Register Calling Convention defines a new behavior for v64i1 types. This type should be saved in GPR. However for 32 bit machine we need to split the value into 2 GPRs (because each is 32 bit). Differential Revision: https://reviews.llvm.org/D26181 llvm-svn: 287217
61 lines
2.2 KiB
C++
61 lines
2.2 KiB
C++
//=== X86CallingConv.cpp - X86 Custom Calling Convention Impl -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the implementation of custom routines for the X86
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// Calling Convention that aren't done by tablegen.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/X86MCTargetDesc.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/IR/CallingConv.h"
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namespace llvm {
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bool CC_X86_32_RegCall_Assign2Regs(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags, CCState &State) {
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// List of GPR registers that are available to store values in regcall
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// calling convention.
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static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI,
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X86::ESI};
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// The vector will save all the available registers for allocation.
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SmallVector<unsigned, 5> AvailableRegs;
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// searching for the available registers.
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for (auto Reg : RegList) {
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if (!State.isAllocated(Reg))
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AvailableRegs.push_back(Reg);
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}
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const size_t RequiredGprsUponSplit = 2;
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if (AvailableRegs.size() < RequiredGprsUponSplit)
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return false; // Not enough free registers - continue the search.
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// Allocating the available registers
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for (unsigned I = 0; I < RequiredGprsUponSplit; I++) {
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// Marking the register as located
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unsigned Reg = State.AllocateReg(AvailableRegs[I]);
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// Since we previously made sure that 2 registers are available
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// we expect that a real register number will be returned
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assert(Reg && "Expecting a register will be available");
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// Assign the value to the allocated register
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State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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}
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// Successful in allocating regsiters - stop scanning next rules.
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return true;
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}
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} // End llvm namespace
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