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6f27d8c6b3
Summary: MCTargetDesc/AMDGPUMCTargetDesc.h contains enums for all the instuction and register defintions, which are huge so we only want to include them where needed. This will also make it easier if we want to split the R600 and GCN definitions into separate tablegenerated files. I was unable to remove AMDGPUMCTargetDesc.h from SIMachineFunctionInfo.h because it uses some enums from the header to initialize default values for the SIMachineFunction class, so I ended up having to remove includes of SIMachineFunctionInfo.h from headers too. Reviewers: arsenm, nhaehnle Reviewed By: nhaehnle Subscribers: MatzeB, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D46272 llvm-svn: 332930
954 lines
32 KiB
C++
954 lines
32 KiB
C++
//===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Interface definition for SIInstrInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
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#include "AMDGPUInstrInfo.h"
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#include "SIDefines.h"
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#include "SIRegisterInfo.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Support/Compiler.h"
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#include <cassert>
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#include <cstdint>
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namespace llvm {
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class APInt;
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class MachineRegisterInfo;
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class RegScavenger;
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class SISubtarget;
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class TargetRegisterClass;
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class SIInstrInfo final : public AMDGPUInstrInfo {
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private:
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const SIRegisterInfo RI;
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const SISubtarget &ST;
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// The inverse predicate should have the negative value.
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enum BranchPredicate {
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INVALID_BR = 0,
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SCC_TRUE = 1,
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SCC_FALSE = -1,
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VCCNZ = 2,
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VCCZ = -2,
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EXECNZ = -3,
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EXECZ = 3
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};
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using SetVectorType = SmallSetVector<MachineInstr *, 32>;
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static unsigned getBranchOpcode(BranchPredicate Cond);
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static BranchPredicate getBranchPredicate(unsigned Opcode);
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public:
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unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
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MachineRegisterInfo &MRI,
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MachineOperand &SuperReg,
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const TargetRegisterClass *SuperRC,
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unsigned SubIdx,
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const TargetRegisterClass *SubRC) const;
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MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
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MachineRegisterInfo &MRI,
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MachineOperand &SuperReg,
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const TargetRegisterClass *SuperRC,
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unsigned SubIdx,
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const TargetRegisterClass *SubRC) const;
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private:
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void swapOperands(MachineInstr &Inst) const;
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bool moveScalarAddSub(SetVectorType &Worklist,
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MachineInstr &Inst) const;
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void lowerScalarAbs(SetVectorType &Worklist,
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MachineInstr &Inst) const;
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void lowerScalarXnor(SetVectorType &Worklist,
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MachineInstr &Inst) const;
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void splitScalar64BitUnaryOp(SetVectorType &Worklist,
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MachineInstr &Inst, unsigned Opcode) const;
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void splitScalar64BitAddSub(SetVectorType &Worklist,
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MachineInstr &Inst) const;
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void splitScalar64BitBinaryOp(SetVectorType &Worklist,
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MachineInstr &Inst, unsigned Opcode) const;
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void splitScalar64BitBCNT(SetVectorType &Worklist,
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MachineInstr &Inst) const;
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void splitScalar64BitBFE(SetVectorType &Worklist,
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MachineInstr &Inst) const;
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void movePackToVALU(SetVectorType &Worklist,
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MachineRegisterInfo &MRI,
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MachineInstr &Inst) const;
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void addUsersToMoveToVALUWorklist(unsigned Reg, MachineRegisterInfo &MRI,
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SetVectorType &Worklist) const;
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void
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addSCCDefUsersToVALUWorklist(MachineInstr &SCCDefInst,
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SetVectorType &Worklist) const;
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const TargetRegisterClass *
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getDestEquivalentVGPRClass(const MachineInstr &Inst) const;
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bool checkInstOffsetsDoNotOverlap(MachineInstr &MIa, MachineInstr &MIb) const;
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unsigned findUsedSGPR(const MachineInstr &MI, int OpIndices[3]) const;
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protected:
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bool swapSourceModifiers(MachineInstr &MI,
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MachineOperand &Src0, unsigned Src0OpName,
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MachineOperand &Src1, unsigned Src1OpName) const;
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MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
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unsigned OpIdx0,
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unsigned OpIdx1) const override;
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public:
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enum TargetOperandFlags {
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MO_MASK = 0x7,
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MO_NONE = 0,
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// MO_GOTPCREL -> symbol@GOTPCREL -> R_AMDGPU_GOTPCREL.
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MO_GOTPCREL = 1,
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// MO_GOTPCREL32_LO -> symbol@gotpcrel32@lo -> R_AMDGPU_GOTPCREL32_LO.
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MO_GOTPCREL32 = 2,
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MO_GOTPCREL32_LO = 2,
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// MO_GOTPCREL32_HI -> symbol@gotpcrel32@hi -> R_AMDGPU_GOTPCREL32_HI.
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MO_GOTPCREL32_HI = 3,
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// MO_REL32_LO -> symbol@rel32@lo -> R_AMDGPU_REL32_LO.
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MO_REL32 = 4,
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MO_REL32_LO = 4,
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// MO_REL32_HI -> symbol@rel32@hi -> R_AMDGPU_REL32_HI.
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MO_REL32_HI = 5
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};
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explicit SIInstrInfo(const SISubtarget &ST);
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const SIRegisterInfo &getRegisterInfo() const {
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return RI;
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}
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bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
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AliasAnalysis *AA) const override;
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bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
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int64_t &Offset1,
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int64_t &Offset2) const override;
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bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
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int64_t &Offset,
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const TargetRegisterInfo *TRI) const final;
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bool shouldClusterMemOps(MachineInstr &FirstLdSt, unsigned BaseReg1,
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MachineInstr &SecondLdSt, unsigned BaseReg2,
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unsigned NumLoads) const final;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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unsigned calculateLDSSpillAddress(MachineBasicBlock &MBB, MachineInstr &MI,
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RegScavenger *RS, unsigned TmpReg,
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unsigned Offset, unsigned Size) const;
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void materializeImmediate(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const DebugLoc &DL,
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unsigned DestReg,
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int64_t Value) const;
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const TargetRegisterClass *getPreferredSelectRegClass(
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unsigned Size) const;
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unsigned insertNE(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I, const DebugLoc &DL,
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unsigned SrcReg, int Value) const;
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unsigned insertEQ(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I, const DebugLoc &DL,
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unsigned SrcReg, int Value) const;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, unsigned SrcReg,
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bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, unsigned DestReg,
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int FrameIndex, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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bool expandPostRAPseudo(MachineInstr &MI) const override;
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// Returns an opcode that can be used to move a value to a \p DstRC
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// register. If there is no hardware instruction that can store to \p
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// DstRC, then AMDGPU::COPY is returned.
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unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
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LLVM_READONLY
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int commuteOpcode(unsigned Opc) const;
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LLVM_READONLY
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inline int commuteOpcode(const MachineInstr &MI) const {
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return commuteOpcode(MI.getOpcode());
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}
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bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
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unsigned &SrcOpIdx2) const override;
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bool isBranchOffsetInRange(unsigned BranchOpc,
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int64_t BrOffset) const override;
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MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
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unsigned insertIndirectBranch(MachineBasicBlock &MBB,
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MachineBasicBlock &NewDestBB,
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const DebugLoc &DL,
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int64_t BrOffset,
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RegScavenger *RS = nullptr) const override;
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bool analyzeBranchImpl(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const;
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify = false) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded = nullptr) const override;
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bool reverseBranchCondition(
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SmallVectorImpl<MachineOperand> &Cond) const override;
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bool canInsertSelect(const MachineBasicBlock &MBB,
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ArrayRef<MachineOperand> Cond,
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unsigned TrueReg, unsigned FalseReg,
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int &CondCycles,
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int &TrueCycles, int &FalseCycles) const override;
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void insertSelect(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, const DebugLoc &DL,
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unsigned DstReg, ArrayRef<MachineOperand> Cond,
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unsigned TrueReg, unsigned FalseReg) const override;
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void insertVectorSelect(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, const DebugLoc &DL,
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unsigned DstReg, ArrayRef<MachineOperand> Cond,
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unsigned TrueReg, unsigned FalseReg) const;
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unsigned getAddressSpaceForPseudoSourceKind(
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PseudoSourceValue::PSVKind Kind) const override;
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bool
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areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
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AliasAnalysis *AA = nullptr) const override;
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bool isFoldableCopy(const MachineInstr &MI) const;
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bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
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MachineRegisterInfo *MRI) const final;
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unsigned getMachineCSELookAheadLimit() const override { return 500; }
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MachineInstr *convertToThreeAddress(MachineFunction::iterator &MBB,
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MachineInstr &MI,
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LiveVariables *LV) const override;
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bool isSchedulingBoundary(const MachineInstr &MI,
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const MachineBasicBlock *MBB,
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const MachineFunction &MF) const override;
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static bool isSALU(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::SALU;
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}
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bool isSALU(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SALU;
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}
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static bool isVALU(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::VALU;
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}
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bool isVALU(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VALU;
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}
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static bool isVMEM(const MachineInstr &MI) {
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return isMUBUF(MI) || isMTBUF(MI) || isMIMG(MI);
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}
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bool isVMEM(uint16_t Opcode) const {
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return isMUBUF(Opcode) || isMTBUF(Opcode) || isMIMG(Opcode);
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}
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static bool isSOP1(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
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}
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bool isSOP1(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SOP1;
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}
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static bool isSOP2(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
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}
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bool isSOP2(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SOP2;
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}
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static bool isSOPC(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
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}
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bool isSOPC(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SOPC;
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}
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static bool isSOPK(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
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}
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bool isSOPK(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SOPK;
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}
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static bool isSOPP(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
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}
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bool isSOPP(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SOPP;
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}
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static bool isVOP1(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
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}
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bool isVOP1(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOP1;
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}
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static bool isVOP2(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
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}
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bool isVOP2(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOP2;
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}
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static bool isVOP3(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::VOP3;
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}
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bool isVOP3(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOP3;
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}
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static bool isSDWA(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
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}
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bool isSDWA(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SDWA;
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}
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static bool isVOPC(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
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}
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bool isVOPC(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::VOPC;
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}
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static bool isMUBUF(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
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}
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bool isMUBUF(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
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}
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static bool isMTBUF(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
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}
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bool isMTBUF(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
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}
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static bool isSMRD(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
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}
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bool isSMRD(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::SMRD;
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}
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bool isBufferSMRD(const MachineInstr &MI) const;
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static bool isDS(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::DS;
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}
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bool isDS(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::DS;
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}
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static bool isMIMG(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
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}
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bool isMIMG(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::MIMG;
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}
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static bool isGather4(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
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}
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bool isGather4(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::Gather4;
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}
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static bool isD16(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::D16;
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}
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bool isD16(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::D16;
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}
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static bool isFLAT(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::FLAT;
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}
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// Is a FLAT encoded instruction which accesses a specific segment,
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// i.e. global_* or scratch_*.
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static bool isSegmentSpecificFLAT(const MachineInstr &MI) {
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auto Flags = MI.getDesc().TSFlags;
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return (Flags & SIInstrFlags::FLAT) && !(Flags & SIInstrFlags::LGKM_CNT);
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}
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// Any FLAT encoded instruction, including global_* and scratch_*.
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bool isFLAT(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::FLAT;
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}
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static bool isEXP(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::EXP;
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}
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bool isEXP(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::EXP;
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}
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static bool isWQM(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::WQM;
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}
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bool isWQM(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::WQM;
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}
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static bool isDisableWQM(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::DisableWQM;
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}
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bool isDisableWQM(uint16_t Opcode) const {
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return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
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}
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static bool isVGPRSpill(const MachineInstr &MI) {
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return MI.getDesc().TSFlags & SIInstrFlags::VGPRSpill;
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}
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|
|
|
bool isVGPRSpill(uint16_t Opcode) const {
|
|
return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill;
|
|
}
|
|
|
|
static bool isSGPRSpill(const MachineInstr &MI) {
|
|
return MI.getDesc().TSFlags & SIInstrFlags::SGPRSpill;
|
|
}
|
|
|
|
bool isSGPRSpill(uint16_t Opcode) const {
|
|
return get(Opcode).TSFlags & SIInstrFlags::SGPRSpill;
|
|
}
|
|
|
|
static bool isDPP(const MachineInstr &MI) {
|
|
return MI.getDesc().TSFlags & SIInstrFlags::DPP;
|
|
}
|
|
|
|
bool isDPP(uint16_t Opcode) const {
|
|
return get(Opcode).TSFlags & SIInstrFlags::DPP;
|
|
}
|
|
|
|
static bool isVOP3P(const MachineInstr &MI) {
|
|
return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
|
|
}
|
|
|
|
bool isVOP3P(uint16_t Opcode) const {
|
|
return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
|
|
}
|
|
|
|
static bool isVINTRP(const MachineInstr &MI) {
|
|
return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
|
|
}
|
|
|
|
bool isVINTRP(uint16_t Opcode) const {
|
|
return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
|
|
}
|
|
|
|
static bool isScalarUnit(const MachineInstr &MI) {
|
|
return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD);
|
|
}
|
|
|
|
static bool usesVM_CNT(const MachineInstr &MI) {
|
|
return MI.getDesc().TSFlags & SIInstrFlags::VM_CNT;
|
|
}
|
|
|
|
static bool usesLGKM_CNT(const MachineInstr &MI) {
|
|
return MI.getDesc().TSFlags & SIInstrFlags::LGKM_CNT;
|
|
}
|
|
|
|
static bool sopkIsZext(const MachineInstr &MI) {
|
|
return MI.getDesc().TSFlags & SIInstrFlags::SOPK_ZEXT;
|
|
}
|
|
|
|
bool sopkIsZext(uint16_t Opcode) const {
|
|
return get(Opcode).TSFlags & SIInstrFlags::SOPK_ZEXT;
|
|
}
|
|
|
|
/// \returns true if this is an s_store_dword* instruction. This is more
|
|
/// specific than than isSMEM && mayStore.
|
|
static bool isScalarStore(const MachineInstr &MI) {
|
|
return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE;
|
|
}
|
|
|
|
bool isScalarStore(uint16_t Opcode) const {
|
|
return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
|
|
}
|
|
|
|
static bool isFixedSize(const MachineInstr &MI) {
|
|
return MI.getDesc().TSFlags & SIInstrFlags::FIXED_SIZE;
|
|
}
|
|
|
|
bool isFixedSize(uint16_t Opcode) const {
|
|
return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
|
|
}
|
|
|
|
static bool hasFPClamp(const MachineInstr &MI) {
|
|
return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
|
|
}
|
|
|
|
bool hasFPClamp(uint16_t Opcode) const {
|
|
return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
|
|
}
|
|
|
|
static bool hasIntClamp(const MachineInstr &MI) {
|
|
return MI.getDesc().TSFlags & SIInstrFlags::IntClamp;
|
|
}
|
|
|
|
uint64_t getClampMask(const MachineInstr &MI) const {
|
|
const uint64_t ClampFlags = SIInstrFlags::FPClamp |
|
|
SIInstrFlags::IntClamp |
|
|
SIInstrFlags::ClampLo |
|
|
SIInstrFlags::ClampHi;
|
|
return MI.getDesc().TSFlags & ClampFlags;
|
|
}
|
|
|
|
bool isVGPRCopy(const MachineInstr &MI) const {
|
|
assert(MI.isCopy());
|
|
unsigned Dest = MI.getOperand(0).getReg();
|
|
const MachineFunction &MF = *MI.getParent()->getParent();
|
|
const MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
return !RI.isSGPRReg(MRI, Dest);
|
|
}
|
|
|
|
bool isInlineConstant(const APInt &Imm) const;
|
|
|
|
bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
|
|
|
|
bool isInlineConstant(const MachineOperand &MO,
|
|
const MCOperandInfo &OpInfo) const {
|
|
return isInlineConstant(MO, OpInfo.OperandType);
|
|
}
|
|
|
|
/// \p returns true if \p UseMO is substituted with \p DefMO in \p MI it would
|
|
/// be an inline immediate.
|
|
bool isInlineConstant(const MachineInstr &MI,
|
|
const MachineOperand &UseMO,
|
|
const MachineOperand &DefMO) const {
|
|
assert(UseMO.getParent() == &MI);
|
|
int OpIdx = MI.getOperandNo(&UseMO);
|
|
if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands) {
|
|
return false;
|
|
}
|
|
|
|
return isInlineConstant(DefMO, MI.getDesc().OpInfo[OpIdx]);
|
|
}
|
|
|
|
/// \p returns true if the operand \p OpIdx in \p MI is a valid inline
|
|
/// immediate.
|
|
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const {
|
|
const MachineOperand &MO = MI.getOperand(OpIdx);
|
|
return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
|
|
}
|
|
|
|
bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx,
|
|
const MachineOperand &MO) const {
|
|
if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands)
|
|
return false;
|
|
|
|
if (MI.isCopy()) {
|
|
unsigned Size = getOpSize(MI, OpIdx);
|
|
assert(Size == 8 || Size == 4);
|
|
|
|
uint8_t OpType = (Size == 8) ?
|
|
AMDGPU::OPERAND_REG_IMM_INT64 : AMDGPU::OPERAND_REG_IMM_INT32;
|
|
return isInlineConstant(MO, OpType);
|
|
}
|
|
|
|
return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType);
|
|
}
|
|
|
|
bool isInlineConstant(const MachineOperand &MO) const {
|
|
const MachineInstr *Parent = MO.getParent();
|
|
return isInlineConstant(*Parent, Parent->getOperandNo(&MO));
|
|
}
|
|
|
|
bool isLiteralConstant(const MachineOperand &MO,
|
|
const MCOperandInfo &OpInfo) const {
|
|
return MO.isImm() && !isInlineConstant(MO, OpInfo.OperandType);
|
|
}
|
|
|
|
bool isLiteralConstant(const MachineInstr &MI, int OpIdx) const {
|
|
const MachineOperand &MO = MI.getOperand(OpIdx);
|
|
return MO.isImm() && !isInlineConstant(MI, OpIdx);
|
|
}
|
|
|
|
// Returns true if this operand could potentially require a 32-bit literal
|
|
// operand, but not necessarily. A FrameIndex for example could resolve to an
|
|
// inline immediate value that will not require an additional 4-bytes; this
|
|
// assumes that it will.
|
|
bool isLiteralConstantLike(const MachineOperand &MO,
|
|
const MCOperandInfo &OpInfo) const;
|
|
|
|
bool isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
|
|
const MachineOperand &MO) const;
|
|
|
|
/// Return true if this 64-bit VALU instruction has a 32-bit encoding.
|
|
/// This function will return false if you pass it a 32-bit instruction.
|
|
bool hasVALU32BitEncoding(unsigned Opcode) const;
|
|
|
|
/// Returns true if this operand uses the constant bus.
|
|
bool usesConstantBus(const MachineRegisterInfo &MRI,
|
|
const MachineOperand &MO,
|
|
const MCOperandInfo &OpInfo) const;
|
|
|
|
/// Return true if this instruction has any modifiers.
|
|
/// e.g. src[012]_mod, omod, clamp.
|
|
bool hasModifiers(unsigned Opcode) const;
|
|
|
|
bool hasModifiersSet(const MachineInstr &MI,
|
|
unsigned OpName) const;
|
|
bool hasAnyModifiersSet(const MachineInstr &MI) const;
|
|
|
|
bool verifyInstruction(const MachineInstr &MI,
|
|
StringRef &ErrInfo) const override;
|
|
|
|
unsigned getVALUOp(const MachineInstr &MI) const;
|
|
|
|
/// Return the correct register class for \p OpNo. For target-specific
|
|
/// instructions, this will return the register class that has been defined
|
|
/// in tablegen. For generic instructions, like REG_SEQUENCE it will return
|
|
/// the register class of its machine operand.
|
|
/// to infer the correct register class base on the other operands.
|
|
const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
|
|
unsigned OpNo) const;
|
|
|
|
/// Return the size in bytes of the operand OpNo on the given
|
|
// instruction opcode.
|
|
unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
|
|
const MCOperandInfo &OpInfo = get(Opcode).OpInfo[OpNo];
|
|
|
|
if (OpInfo.RegClass == -1) {
|
|
// If this is an immediate operand, this must be a 32-bit literal.
|
|
assert(OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE);
|
|
return 4;
|
|
}
|
|
|
|
return RI.getRegSizeInBits(*RI.getRegClass(OpInfo.RegClass)) / 8;
|
|
}
|
|
|
|
/// This form should usually be preferred since it handles operands
|
|
/// with unknown register classes.
|
|
unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
|
|
return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
|
|
}
|
|
|
|
/// \returns true if it is legal for the operand at index \p OpNo
|
|
/// to read a VGPR.
|
|
bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const;
|
|
|
|
/// Legalize the \p OpIndex operand of this instruction by inserting
|
|
/// a MOV. For example:
|
|
/// ADD_I32_e32 VGPR0, 15
|
|
/// to
|
|
/// MOV VGPR1, 15
|
|
/// ADD_I32_e32 VGPR0, VGPR1
|
|
///
|
|
/// If the operand being legalized is a register, then a COPY will be used
|
|
/// instead of MOV.
|
|
void legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const;
|
|
|
|
/// Check if \p MO is a legal operand if it was the \p OpIdx Operand
|
|
/// for \p MI.
|
|
bool isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
|
|
const MachineOperand *MO = nullptr) const;
|
|
|
|
/// Check if \p MO would be a valid operand for the given operand
|
|
/// definition \p OpInfo. Note this does not attempt to validate constant bus
|
|
/// restrictions (e.g. literal constant usage).
|
|
bool isLegalVSrcOperand(const MachineRegisterInfo &MRI,
|
|
const MCOperandInfo &OpInfo,
|
|
const MachineOperand &MO) const;
|
|
|
|
/// Check if \p MO (a register operand) is a legal register for the
|
|
/// given operand description.
|
|
bool isLegalRegOperand(const MachineRegisterInfo &MRI,
|
|
const MCOperandInfo &OpInfo,
|
|
const MachineOperand &MO) const;
|
|
|
|
/// Legalize operands in \p MI by either commuting it or inserting a
|
|
/// copy of src1.
|
|
void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr &MI) const;
|
|
|
|
/// Fix operands in \p MI to satisfy constant bus requirements.
|
|
void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr &MI) const;
|
|
|
|
/// Copy a value from a VGPR (\p SrcReg) to SGPR. This function can only
|
|
/// be used when it is know that the value in SrcReg is same across all
|
|
/// threads in the wave.
|
|
/// \returns The SGPR register that \p SrcReg was copied to.
|
|
unsigned readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr &UseMI,
|
|
MachineRegisterInfo &MRI) const;
|
|
|
|
void legalizeOperandsSMRD(MachineRegisterInfo &MRI, MachineInstr &MI) const;
|
|
|
|
void legalizeGenericOperand(MachineBasicBlock &InsertMBB,
|
|
MachineBasicBlock::iterator I,
|
|
const TargetRegisterClass *DstRC,
|
|
MachineOperand &Op, MachineRegisterInfo &MRI,
|
|
const DebugLoc &DL) const;
|
|
|
|
/// Legalize all operands in this instruction. This function may
|
|
/// create new instruction and insert them before \p MI.
|
|
void legalizeOperands(MachineInstr &MI) const;
|
|
|
|
/// Replace this instruction's opcode with the equivalent VALU
|
|
/// opcode. This function will also move the users of \p MI to the
|
|
/// VALU if necessary.
|
|
void moveToVALU(MachineInstr &MI) const;
|
|
|
|
void insertWaitStates(MachineBasicBlock &MBB,MachineBasicBlock::iterator MI,
|
|
int Count) const;
|
|
|
|
void insertNoop(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI) const override;
|
|
|
|
void insertReturn(MachineBasicBlock &MBB) const;
|
|
/// Return the number of wait states that result from executing this
|
|
/// instruction.
|
|
unsigned getNumWaitStates(const MachineInstr &MI) const;
|
|
|
|
/// Returns the operand named \p Op. If \p MI does not have an
|
|
/// operand named \c Op, this function returns nullptr.
|
|
LLVM_READONLY
|
|
MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
|
|
|
|
LLVM_READONLY
|
|
const MachineOperand *getNamedOperand(const MachineInstr &MI,
|
|
unsigned OpName) const {
|
|
return getNamedOperand(const_cast<MachineInstr &>(MI), OpName);
|
|
}
|
|
|
|
/// Get required immediate operand
|
|
int64_t getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const {
|
|
int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OpName);
|
|
return MI.getOperand(Idx).getImm();
|
|
}
|
|
|
|
uint64_t getDefaultRsrcDataFormat() const;
|
|
uint64_t getScratchRsrcWords23() const;
|
|
|
|
bool isLowLatencyInstruction(const MachineInstr &MI) const;
|
|
bool isHighLatencyInstruction(const MachineInstr &MI) const;
|
|
|
|
/// Return the descriptor of the target-specific machine instruction
|
|
/// that corresponds to the specified pseudo or native opcode.
|
|
const MCInstrDesc &getMCOpcodeFromPseudo(unsigned Opcode) const {
|
|
return get(pseudoToMCOpcode(Opcode));
|
|
}
|
|
|
|
unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
|
|
unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
|
|
|
|
unsigned isLoadFromStackSlot(const MachineInstr &MI,
|
|
int &FrameIndex) const override;
|
|
unsigned isStoreToStackSlot(const MachineInstr &MI,
|
|
int &FrameIndex) const override;
|
|
|
|
unsigned getInstBundleSize(const MachineInstr &MI) const;
|
|
unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
|
|
|
|
bool mayAccessFlatAddressSpace(const MachineInstr &MI) const;
|
|
|
|
bool isNonUniformBranchInstr(MachineInstr &Instr) const;
|
|
|
|
void convertNonUniformIfRegion(MachineBasicBlock *IfEntry,
|
|
MachineBasicBlock *IfEnd) const;
|
|
|
|
void convertNonUniformLoopRegion(MachineBasicBlock *LoopEntry,
|
|
MachineBasicBlock *LoopEnd) const;
|
|
|
|
std::pair<unsigned, unsigned>
|
|
decomposeMachineOperandsTargetFlags(unsigned TF) const override;
|
|
|
|
ArrayRef<std::pair<int, const char *>>
|
|
getSerializableTargetIndices() const override;
|
|
|
|
ArrayRef<std::pair<unsigned, const char *>>
|
|
getSerializableDirectMachineOperandTargetFlags() const override;
|
|
|
|
ScheduleHazardRecognizer *
|
|
CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
|
|
const ScheduleDAG *DAG) const override;
|
|
|
|
ScheduleHazardRecognizer *
|
|
CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const override;
|
|
|
|
bool isBasicBlockPrologue(const MachineInstr &MI) const override;
|
|
|
|
/// Return a partially built integer add instruction without carry.
|
|
/// Caller must add source operands.
|
|
/// For pre-GFX9 it will generate unused carry destination operand.
|
|
/// TODO: After GFX9 it should return a no-carry operation.
|
|
MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
const DebugLoc &DL,
|
|
unsigned DestReg) const;
|
|
|
|
static bool isKillTerminator(unsigned Opcode);
|
|
const MCInstrDesc &getKillTerminatorFromPseudo(unsigned Opcode) const;
|
|
|
|
static bool isLegalMUBUFImmOffset(unsigned Imm) {
|
|
return isUInt<12>(Imm);
|
|
}
|
|
};
|
|
|
|
namespace AMDGPU {
|
|
|
|
LLVM_READONLY
|
|
int getVOPe64(uint16_t Opcode);
|
|
|
|
LLVM_READONLY
|
|
int getVOPe32(uint16_t Opcode);
|
|
|
|
LLVM_READONLY
|
|
int getSDWAOp(uint16_t Opcode);
|
|
|
|
LLVM_READONLY
|
|
int getBasicFromSDWAOp(uint16_t Opcode);
|
|
|
|
LLVM_READONLY
|
|
int getCommuteRev(uint16_t Opcode);
|
|
|
|
LLVM_READONLY
|
|
int getCommuteOrig(uint16_t Opcode);
|
|
|
|
LLVM_READONLY
|
|
int getAddr64Inst(uint16_t Opcode);
|
|
|
|
LLVM_READONLY
|
|
int getMUBUFNoLdsInst(uint16_t Opcode);
|
|
|
|
LLVM_READONLY
|
|
int getAtomicRetOp(uint16_t Opcode);
|
|
|
|
LLVM_READONLY
|
|
int getAtomicNoRetOp(uint16_t Opcode);
|
|
|
|
LLVM_READONLY
|
|
int getSOPKOp(uint16_t Opcode);
|
|
|
|
const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
|
|
const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19);
|
|
const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21);
|
|
const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
|
|
|
|
// For MachineOperands.
|
|
enum TargetFlags {
|
|
TF_LONG_BRANCH_FORWARD = 1 << 0,
|
|
TF_LONG_BRANCH_BACKWARD = 1 << 1
|
|
};
|
|
|
|
} // end namespace AMDGPU
|
|
|
|
namespace SI {
|
|
namespace KernelInputOffsets {
|
|
|
|
/// Offsets in bytes from the start of the input buffer
|
|
enum Offsets {
|
|
NGROUPS_X = 0,
|
|
NGROUPS_Y = 4,
|
|
NGROUPS_Z = 8,
|
|
GLOBAL_SIZE_X = 12,
|
|
GLOBAL_SIZE_Y = 16,
|
|
GLOBAL_SIZE_Z = 20,
|
|
LOCAL_SIZE_X = 24,
|
|
LOCAL_SIZE_Y = 28,
|
|
LOCAL_SIZE_Z = 32
|
|
};
|
|
|
|
} // end namespace KernelInputOffsets
|
|
} // end namespace SI
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif // LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
|